Dynamic storage synchronizer using variable oscillator and FIFO buffer

DETAILED DESCRIPTION The present invention adds a variable rate oscillator and a FIFO buffer to a dynamic storage subsystem based upon CCD or an analogous technology.
The rate at which the dynamic storage subsystem is clocked is controlled by the variable rate oscillator.
At such times as no access request is being honored, the variable rate oscillator clocks the dynamic storage subsystem at some minimum rate consistent with reliable operation in order to conserve power and extend the life of the storage devices.
Upon receiving an access request, the variable rate oscillator increases its frequency to the maximum rate until the dynamic storage subsystem is ready to access the desired addressable locations.
This readiness is determined by matching the requested address with the dynamic storage subsystem current address.
If a write access has been requested, the variable rate oscillator changes to the minimum rate after the match is found.
If a read access has been requested, the variable rate oscillator remains at the maximum rate.
Data transfers to and from the dynamic storage subsystem are via the FIFO buffer.
For a write access, data is transferred from the requestor to the FIFO buffer at a rate determined by the requestor.
The data is then transferred from the FIFO buffer to the dynamic storage subsystem at a rate determined by the variable rate oscillator.
For a read access, data is transferred from the dynamic storage subsystem to the FIFO buffer at a rate determined by the variable rate oscillator.
The data is then transferred from the FIFO buffer to the requestor at a rate determined by the requestor.
During the time that data is being transferred to and from the FIFO buffer, the frequency of the variable rate oscillator is determined by the amount of data currently resident in the FIFO buffer.
For write accesses, the more data resident in the FIFO buffer, the higher the frequency of the variable rate oscillator tending to decrease the quantity of data in the FIFO buffer.
The less data resident in the FIFO buffer, the lower the frequency of the variable rate oscillator, tending to increase the quantity of data in the FIFO buffer