Ensuring data integrity by locked-load and conditional-store operations in a multiprocessor system

DETAILED DESCRIPTION In accordance with one embodiment of the invention, a high-performance processor is provided which is of the RISC type, using a standardized, fixed instruction size, and permitting only a simplified memory access data width, using simple addressing modes.
The instruction set is limited to register-to-register operations (for arithmetic and logic type operations using the ALU, etc.
) and register load/store operations where memory is referenced; there are no memory-to-memory operations, nor register-to-memory operations in which the ALU or other logic functions are done.
The functions performed by instructions are limited to allow non-microcoded implementation, simple to decode and execute in a short cycle.
On-chip floating point processing is provided, and on-chip instruction and data caches are employed in an example embodiment.
Byte manipulation instructions are included to permit use of previously-established data structures.
These instructions include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions, so that byte addresses can be made use of even though the actual memory operations are aligned quadword in nature.
The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes.
To write to a byte address in a multibyte (e.
g.
, quadword) aligned memory, the CPU loads a quadword (or longword) and locks this location, writes to the byte address in register while leaving the remainder of the quadword undisturbed, then stores the updated quadword in memory conditionally, depending upon whether the quadword has been written by another processor since the load/locked operation.
Another byte manipulation instruction, according to one feature of the invention, is a byte compare instruction.
All bytes of a quadword in a register are compared to corresponding bytes in another register.
The result is a single byte (one bit for each byte compared) in a third register