 Clock synchronization algorithm for address independent networks |
| It is therefore an object of the invention to provide a simple clock synchronization algorithm for ... |
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| Method for synchronizing interconnected digital equipment |
| Digital networks are represented as a combination of digital equipment shown as nodes in FIG. 1 ... |
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| Method and apparatus for dispatching tasks requiring short-duration processor affinity |
| To achieve these and other objects, this invention provides a mechanism for efficiently ... |
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| Method of processing sub-images of an image field |
| What I claim is: 1. A method of image processing comprising the steps of: viewing an image field; ... |
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| Deadlock resolution with cache snooping |
| FIG. 1 is a block diagram of a data processing apparatus according to the present invention. It is ... |
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| Dual port memory device with improved serial access scheme |
| OF THE DRAWINGS FIG. 1 is a schematic block diagram of a dual port memory according to a prior art;... |
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| Semiconductor memory device capable of relieving defective bits |
| Accordingly, an object of this invention is to provide a semiconductor memory device in which the ... |
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| Protection circuit for non-volatile memory |
| What is claimed is: 1. A protection circuit for a non-volatile memory comprising: means for ... |
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| Disk cache control unit |
| The object of the present invention is to provide a disk cache control unit which can reduce ... |
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Extended communications link for keyboard and display units remotely located from a computer
| Details |
Inventors: Asprey, Robert R.; Shatas, Remigius G.;
Assignee: Cybex Corporation (Huntsville, AL)
Primary Examiner: Williams, Jr.; Archie E.
Assistant Examiner: Muntheanu; R. Florin
Attorney, Agent or Firm: Phillips; C. A.
A communications extension link for use between a computer and a keyboard and display unit has at the computer site a first interface circuit connected to it and adjacent to the keyboard and display unit a second interface circuit connected to it. The two interface circuits may then be spaced serveral hundred feet by an extension cable. The first interface circuit includes capacitors connected between keyboard data and clock lines and a positive supply terminal, and buffer amplifiers are placed in the signal lines relating to the display unit. The second interface circuit employs discrete resistors between clock and data lines and the positive supply terminal, and between the vertical sync line and logic ground. In addition, capacitance is added between the positive supply terminal and logic ground. |
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DETAILED DESCRIPTION OF THE DRAWING Referring to the drawing, a shielded cable 10 is connected from keyboard input connector terminals 12 of computer 14 to receptacle terminals 16 housed in receptacle assembly 18.
Receptacles 16 connect to plug terminals 17 of plug assembly 19 of signal conditioning circuit 20.
Circuit 20 is located in housing 30 and, as labeled, connections to it are clock (CLK), data (DTA), +5 volts (+5 V) and logic ground (GND).
Cable shield or sheath 32 of metal is connected to both chassis ground 34 of computer 14 and chassis ground 36 of housing 30.
A +5-volt input is coupled from connector terminals 12 from computer 14 via receptacle 16 and plug 17 to lead 37 through fuse 38 to receptacle 40 of receptacle assembly 41.
Receptacle 40 is coupled to plug 42 of plug assembly 43, which in turn couples the +5 v.
to shielded cable 110.
The clock, data, and logic ground leads are similarly connected between like labeled connector terminals 12 to receptacles 16 and plugs 17, which are directly connected to receptacles 40 and plugs 42.
Significantly, it has been discovered that interference between the video lines and clock and data lines is substantially reduced by employment of capacitors 44 and 46, capacitor 44 being connected from clock lead 48 to the +5-volt lead 37 and capacitor 46 connected from data lead 52 to +5-volt lead 37.
Capacitor 44 has a value of approximately 0.
002 mfd, and capacitor 46 has a value of up to approximately 0.
006 mfd.
In addition, a relatively large capacitor 54, for example, 22 mf, is connected between +5-volt lead 37 and logic ground; and a smaller capacitor 56, for example, 0.
1 mf, is also connected between these points.
By this means, high frequency noise is shunted to ground via the smaller, faster-acting capacitor.
The larger and slower-acting one is used to stablize the +5-v.
D.
C.
supply.
A second shielded cable 60 is connected from monitor output connector terminals 62 of computer 14 to functionally labeled receptacle terminals 63 mounted in receptacle assembly 66 and which connect to plug terminals 64 mounted in plug assembly 67 of signal conditioning circuit 20
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