FIFO Register with independent clocking means

DETAILED DESCRIPTION This invention is a special pointer register which is used with a system having two interfacing system portions which have different operating speeds.
This register permits data to be clocked into one side of a RAM or register, and, as well, to be clocked out of the other end of the register or RAM in a "first-in, first-out" (FIFO) manner.
Basically, the system gives the appearance of one or more logic blocks which resemble D-type flip-flops.
Each of the logic blocks is independently clocked.
The system is initialized to store a prescribed code therein.
The circuit then is operated upon to interpret the initialized condition and to copy a portion of the coded data into the next logic block.
The coded data is then interrogated or tested to determine what, if any, activity can next be taken.
Under appropriate conditions, the copying operation continues.
With the sensing of prescribed coded conditions, the operation of the register is specifically controlled.
For example, the register prevents the writing of data into a full memory register or the reading of data or information from an empty memory or register.
Of course, in the absence of one of these unacceptable conditions, the register will continue to function and to clock data from the input end to the output end at its own rate of speed which is independent of either the input or the output device.
Moreover, the reading and writing operations can take place in the same register on a basically random arrangement so long as the forbidden or unacceptable conditions noted above are avoided.