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| Non-volatile, electrically erasable and reprogrammable memory element |
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| High speed processing flip-flop |
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| Compact multifunction logic circuit |
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| Semiconductor storage device with redundancy arrangement |
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| Broadband signal switching matrix network |
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| Programmable logic module and architecture for field programmable gate array device |
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Facsimile/telephone controller
| Details |
Inventors: Greenstein, Harvey; Levinski, Charles B.; Newman, Edward; Persel, John M.; Widmann, David N.;
Assignee: Hecon Corporation (Eatontown, NJ)
Primary Examiner: Ng; Jin F.
Assistant Examiner: Woo; Stella L.
Attorney, Agent or Firm: Weinstein; Louis
A microprocessor/based telephone/facsimile controller which automatically gives priority to incoming messages. The ring voltage of an incoming message causes the microprocessor to close and latch the line between the telephone and the facsimile. When transmission is completed, the line is dropped and this condition is sensed causing the latch relay to open to prevent the facsimile from transmitting, no data being logged for incoming facsimile transmissions. Only a valid input code permits the coupling of the facsimile to the telephone line also initiating a timer. A broadcast mode latches the telephone line to permit delayed calls and multiple facsimile transmissions, each allocated to the user code which established the broadcast mode. A default time is utilized to accommodate the redial and use of the line for non-facsimile telephone transmission. |
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DETAILED DESCRIPTION OF THE INVENTION FIGS.
1a and 1b show a line sensing relay 14 and a double pole single throw latch relay 16 coupled between a telephone line 10 and a facsimile machine 12.
Latch relay 16 is capable of maintaining either state to which it is driven (open or closed) when driven by a single pulse of short duration.
A ring detector 18 is coupled across the pair of lines extending between the telephone line 10 and facsimile machine 12 and is provided with an opto-isolator 18a for coupling an output signal through circuit 20 to microprocessor connector 22.
A tone receiver 24 is coupled across lines L1, L2 by transformer T and provides a four-bit binary output for transmission of each tone to the microprocessor by interface circuit 26 and connector 22.
A 2100 Hz.
detector circuit 28, coupled to power supply 30 monitors lines L1, L2 through isolation transformer T and couples its output to a phase locked loop 32 utilized by the 2100 Hz.
detector.
The output signal of the phase locked loop 32 is coupled to the interface circuit 26.
The line sense relay 14 detects a pick-up condition and couples this condition to the microprocessor connector through amplifiers 34 and 36.
Monostable multivibrator circuits 38 and 40 are coupled to the control windings of latch relay 16 by transistors Q1 and Q2, respectively The controller 50, shown in FIGS.
2a and 2b, is comprised of microprocessor 52, latch circuit 54, EPROM 56, latch 58, display means 60, key pad 62, latch 64, printer 66, serial printer port 68, battery power supply controller 70, interrupt controller chip 72, random access memory (RAM) 74, address controller 76, address decoder 78, real time clock 80, analog switches 82, 84, 86 and 88, connector 90 and gates 92 and 94.
The CPU 52 controls the entire system including that shown in both FIGS.
1a, 1b and 2a, 2b.
The operating programs are stored in EPROM 56.
To transmit a facsimile message, key pad 62 is operated.
It should be understood that key pad 62 is a key pad having at least the keys "zero through nine" as well as some alphabetic and function keys, if desired
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I/O Systems 
