Flat-cell read-only-memory integrated circuit

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A detailed description of the preferred embodiments of the present invention is described with reference to FIGS.
1-8.
FIGS.
1-3 illustrate the flat-cell ROM layout and basic circuit of the prior art.
FIG.
4 is a schematic diagram of one ROM sub-array according to the present invention.
FIGS.
5-7 illustrate the layout of the ROM sub-array according to the present invention.
FIG.
8 is a schematic diagram of a ROM sub-array according to the present invention with isolated block select transistors on each end of the local bit lines.
I.
Flat Cell Design The manufacturing technique for the flat-cell is illustrated in FIGS.
1, 2A, 2B, and 3.
In FIG.
1, a schematic diagram of the layout from the top view of four-transistor flat-cell array is shown.
The horizontal bars 10 and 11 are polysilicon word lines.
The vertical bars 12, 13, and 14, are buried n+ diffusion regions.
The regions C1, C2, C3 and C4 are the gate/channel regions of respective flat-cell transistors which store data, and form the ROM cell storage unit.
In order to store 1 or 0 in each of the transistors, a mask ROM technique is used to lay down low enhancement or high enhancement type channels.
FIGS.
2A and 2B are cross sectional views of the flat-cell array of FIG.
1.
FIG.
2A shows a cross section taken along the line 2A--2A in the polysilicon word line 10.
As can be seen, the buried diffusion lines 12, 13, and 14 are deposited in the silicon substrate.
A thin gate oxide 16 is deposited over the silicon substrate.
Then polysilicon word lines are deposited over the gate oxide.
FIG.
2B shows a cross section of the array of FIG.
1, taken through along the line 2B--2B in the buried diffusion region 14.
This illustrates the buried diffusion region 14 as a oontinuous n+ doped conductive bit line along the array.
The gate oxide 16 is laid down over the buried diffusion regions, and the polysilicon word lines 10, 11 are deposited over the gate oxide.
FIG.
3 is a circuit diagram which represents the flat-cell structure, in which lines 10 and 11 correspond to the polysilicon word lines 10 and 11 of FIG