Flexible mode DES system

DETAILED DESCRIPTION OF THE INVENTION (The reader should note that nearly all description below applies to encryption of decryption circuits but the explanations are limited, for the most part, to encryption.
) FIG.
2 depicts a block diagram of the invention.
Input/Output register 20, data I/O controller 22 and output MUX and register 24 make up input/output control subsystem 26.
A portion of input register 20 is shown in logic diagram form in FIG.
1.
Flip-flops 1-64 are divided into eight sub-registers R.
sub.
0 -R.
sub.
7.
Each of subregisters R.
sub.
0 -R.
sub.
7 comprise eight flip-flops.
For example, subregister R.
sub.
0 comprises flip-flops 64-57; R.
sub.
1 comprises flip-flops 56-49 and R.
sub.
7 comprises flip-flops 8-1.
Notice that the number assigned to each flip-flop corresponds to a bit number of an input word.
Each flip-flop is associated with a switch or MUX having a corresponding number designation except F/F 64.
For example, the row of MUX's in subregister R.
sub.
0 (which comprises flip-flops 64-57) comprises numbers 63-57.
All of the MUX's 63-1 operate as follows; if "S.
sub.
A " is high (true) the input as "A" appears at output "O".
If "S.
sub.
B " is high, the input at "B" is present at output "O".
The input at "D" of F/F 64 is K.
sub.
7, a serial bit stream.
If "S.
sub.
A " of MUX 63 is true, the output "O" will follow the input at "A".
Note that all "S.
sub.
A "s are connected in common to control signal "Data Serial/Parallel" and that the complement of this signal, developed by inverter 40, is applied to all "S.
sub.
B " inputs of all 63 MUXs 63-1.
When "S.
sub.
A " is true, MUXs 63-1 serve to connect flip-flops 64-1 in series as a single 64 bit long serial shift register.
After 64 input bits are serially shifted into this 64 bit serial register, the first input bit appears at "K.
sub.
1 '" the Q output of flip-flop 1.
When S.
sub.
B goes true, sub-registers R.
sub.
0 -R.
sub.
7 are connected as eight parallel shift registers.
The inputs to sub-register R.
sub.
0, in this case, are bits K.
sub.
7 -K.
sub.
0, as shown in FIG