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Floating point division control
| Details |
Inventors: Wilson, Troy K.; Handly, Robert J.;
Assignee: Honeywell Inc. (Minneapolis, MN)
Primary Examiner: Malzahn; David H.
Assistant Examiner:
Attorney, Agent or Firm: Burton; Lockwood D., Marhoefer; L. J., Hughes; Edward W.
An improved means and method for accomplishing floating point calculations in computational apparatus includes a primary microprocessor and a secondary microprocessor, each with its own control ROM. The normal or fixed point calculations are handled by the primary microprocessor under the control of a first segment of the associated control ROM. When a floating point calculation is called for, a second segment of that ROM is addressed. The addressing of the second segment of the first ROM also effects the coincident addressing of the ROM of the secondary microprocessor. For floating point calculations, the exponent portion of the numbers being manipulated is handled by the primary microprocessor. Simultaneously therewith, the mantissa portion of the numbers being manipulated is handled by the secondary microprocessor under the control of its associated control ROM. The resultant calculations are recombined in the primary microprocessor to produce a complete solution for the floating point calculation. In executing a division operation, the mantissas are preconditioned to be normalized, the most significant bit being a logical "1". The divide routine shifts and subtracts repeatedly until the most significant bit in an accumulating register is also a logical "1", thus eliminating the need for a preset counter and the associated control functions. |
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DETAILED DESCRIPTION It is, accordingly, an object of the present invention to provide an improved means and method for executing a division operation in a floating point calculation.
It is another object of the present invention to provide an improved means and method for effecting a division operation, as set forth, without the use of a preset counter and the associated control circuitry.
In accomplishing these and other objects, there has been provided, in accordance with the present invention, an improved computational apparatus wherein a central processing unit has the usual complement of a memory and a bus control, an arithmetic logic unit with its associated registers, a control ROM having associated control instruction register.
There is provided an additional arithmetic logic unit having its associated registers at a control ROM with its associated control instruction register.
The second ALU is connected as an adjunct to the primary ALU and does not communicate therewith by way of the CPU bus but is, rather, internally connected as an extention of the primary ALU.
The control ROM of the primary ALU is divided into two segments, the first segment being devoted to the normal or fixed point operation of the primary ALU.
The second segment is devoted to the operation of the floating point calculations.
The control ROM of the auxiliary ALU is addressed only when the second segment of the primary control ROM is addressed and is constructed as a bit-extension to increase the effective word length of the addresses in the second segment of the primary control ROM.
While the computer is operating in its normal mode and there arises an occasion for the handling of a floating point calculation, the second segment of the control ROM of the primary ALU and, hence, the control ROM of the auxiliary ALU, is addressed.
The mathmatical values to be manipulated in accordance with the floating point calculations is expressed in terms of so-called scientific notation, that is, M.
times.
2.
sup.
nth.
The exponent portions of the calculation are processed by the primary ALU while the mantissa of the mathmetical expression is manipulated in the auxiliary ALU, both operations may be carried out simultaneously
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I/O Systems 
