Frame register switching for a video processor

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG.
1 shows a block diagram of the video frame register interface 201 of the current invention and how it is connected to other circuitry in a typical environment.
The microprocessor interface 107 serves as the source of control data for the registers.
The microprocessor interface reads digital data which originates from user specifications and workstation system configuration.
The register interface of FIG.
1 has two frame registers, and each frame register is made up of a two-storage element FIFO buffer.
One frame register is made up of storage elements 101 and 102 and the other frame register is made up of storage elements 103 and 104.
Each storage element actually comprises enough memory elements to hold the data required to control an entire frame of image data.
The selector 105 is controlled through a programming interface.
Notice that only the first storage element of each register may receive data from the microprocessor interface, and only the second storage element of each register may output data to the selector 105.
This arrangement allows new control values to be written by the microprocessor at any time without disturbing the control values associated with the current image being displayed.
The output of the selector drives video processing circuitry 106.
This video processing circuitry includes an image processor and other circuitry to be described below.
FIG.
2 shows a block diagram of a video processor chip 200 in which the register interface 201 of FIG.
1 is used.
The microprocessor interface 207 is connected to the microprocessor through a microprocessor bus, and to the frame register interface of FIG.
1, 201.
The frame register interface outputs control data from one register or the other such that control values for the even field are in effect when the even image is being processed and control values for the odd field are in effect when the odd image is being processed.
The video processor integrated circuit chip 200 includes digitizer and codec interfaces 204 and 205, an image processor 202 and a video memory interface 203