 Self timed interface |
| An object of this invention is the provision of a cost effective bus data transfer system that can ... |
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| Digital phase-lock loop control system |
| It is an object of this invention to implement a PLL function. It is also an object of this ... |
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| Data output buffer of a semiconducter memory device |
| It is therefore object of the present invention to provide a semiconductor memory device capable of ... |
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| Synchronous DRAM having a high data transfer rate |
| Accordingly, it is an object of the present invention to provide a semiconductor memory which has ... |
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| High-speed synchronous write control scheme |
| A semiconductor memory device having pairs of data lines for reading and writing data signals to ... |
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| Elasticity buffer for data/clock synchronization |
| OF PREFERRED EMBODIMENT The present invention has application to any data transfer system that ... |
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| Computer systems and methods for pipelined transfer of data between modules |
| Synchronous Global Bus The chief object of the present invention is to perform fast block transfers ... |
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| Dynamic random access memory system |
| It is object of the present invention to minimize the number of address control pins and signal ... |
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| Optical clock distribution system |
| OF THE PREFERRED EMBODIMENT In the following detailed description of the preferred embodiment, ... |
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Full duplex buffer management and apparatus
| Details |
Inventors: Runaldue, Thomas J.; Dwork, Jeffrey Roy;
Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA)
Primary Examiner: Harrell; Robert B.
Assistant Examiner: Coulter; Kenneth R.
Attorney, Agent or Firm: Sawyer & Associates
A node having a system interface adapter for intercoupling a fixed speed bus to a variable latency bus. The system interface adapter includes a receive FIFO buffer memory, a transmit FIFO buffer memory, and a memory buffer management unit. The memory buffer management unit dynamically awards priority between the two FIFOs for access to the variable latency bus in a fashion to minimize overflowing or underflowing the FIFOs while reducing the FIFO sizes. Priority between pending receive data transfers and pending transmit data transfers is resolved, in part, upon a whether a receive operation vis-a-vis the fixed-speed bus is underway. |
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DETAILED DESCRIPTION The present invention provides for a buffer management system to dynamically allocate priority between two buffer memories, a receive memory and a transmit memory, when accessing a storage device having a variable latency.
The invention reduces buffer size and minimizes the number of overflows and underflows.
Further, the invention simply and efficiently reduces the problem of receive lockout of transmission.
The preferred embodiment of the present invention includes a node having a network system interface adapter with a memory buffer management unit, a transmit FIFO buffer memory and receive FIFO buffer memory, and a network interface.
This system interface adapter attaches to a system bus, from which there are also attached a CPU, a storage device and other peripheral devices.
The transmit and receive FIFO buffer memories are sized, in the preferred embodiment, to store about two minimal size data packets.
Network packets can vary in size between 64 and 1518 bytes.
The network interface provides information to the buffer memory management unit regarding whether a receive activity is taking place, while the FIFOs provide information regarding the number of bytes stored and if at least one complete transmit frame is present.
The buffer memory management unit, based upon the information from the FIFOs and the network interface, awards priority to a particular one of the FIFOs, providing it access to the storage device.
In the preferred embodiment, the FIFOs access the storage device through a direct memory access (DMA) burst transfer initiated and controlled by the memory buffer management unit.
The memory buffer management unit prioritizes a pending receive DMA burst transfer over a pending transmit DMA burst transfer dependent upon whether a receive operation is occurring and the status of the fill levels of the receive and transmit FIFO buffer memories.
In operation, the memory buffer management unit will award priority to a pending receive DMA burst transfer over a pending transmit DMA burst transfer as long as the transmit FIFO buffer memory stores one or more frames, and the receive FIFO buffer memory stores a number of bytes greater than a predetermined threshold (that is, it requests to be emptied), while a receive operation is in progress
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I/O Systems 
