Function test evaluation apparatus for evaluating a function test of a logic circuit

DETAILED DESCRIPTION Accordingly, an object of the invention is to provide a function test evaluation apparatus for evaluating the function of an integrated circuit for a short time.
In order to achieve the above object, there is provided a function test evaluation apparatus for evaluating the function of a logic circuit comprising: a control section including a main memory for storing the input test information to be supplied to an integrated circuit to be tested and the expected value information to be outputted from the integrated circuit, and a central processing element for performing various controls; a plurality of memory means which stores the input test information supplied from the main memory of the control section and the expected value information, those information being read out through the addressing; a plurality of write circuit means for writing the input test information outputted from the main memory and the expected value information therefrom; a plurality of address control circuit means for successively supplying the address information to the memory means with given phase differences; parallel-to-serial converting means which is supplied in parallel with the information successively read out from the memory means through the designation by the address control circuit means and which produces the information in serial fashion; pattern format control circuit means which time-shapes the test information outputted serially from the parallel to serial converting circuit means and then supplies it to the circuit to be tested; and a judgement circuit for comparing the expected value information outputted serially from the parallel-to-serial converting circuit with the information outputted from the integrated circuit after it is supplied with the input test information.
This invention will be better understood from the following description taken in connection with the accompanying drawings, in which: