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Gate-array-with-bidirectional-symmetry

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Gate array with bidirectional symmetry

Details

Inventors: Angleton, Joseph L.; Gutgsell, Jeffery L.;
Assignee: Hughes Aircraft Company (Los Angeles, CA)
Primary Examiner: Fears; Terrell W.
Assistant Examiner:
Attorney, Agent or Firm: Brown; Charles D., Karambelas; A. W.

The ease and versatility by which logic functions may be implemented in a semicustom CMOS gate array is substantially increased by disposing core cells within the gate array about a plane of mirror symmetry. Such a gate array is devised with mirror symmetry in two orthogonal directions. A memory design of general utility and with particular utility in a gate array is devised so as to operate with a programmable word length. The word length of the memory is programmed by choosing an appropriate integrated circuit metal mask option to be utilized in the memory circuit design at a data bus input and output mapping. In the event that the memory is entirely included within a large scale integrated circuit, such as a gate array, a circuit design is further devised for providing a self-test of the operability of such a fully included memory without the necessity of providing input/output pins communicating with the memory or other external test signals. The self-test is activated by applying a single external start signal at a corresponding single external circuit pin with an indication of failure at any point during a complete memory test cycle being coupled to a second external failure pin. A self-test protocol is utilized wherein an internal counter generates the addresses of each memory location and stores that address as data within the memory location and the inverse of the address as data. In each case, what was then written into the memory is compared to that which is later read from the memory to thereby validate operability of the memory.

DETAILED DESCRIPTION The invention is an improvement in a CMOS gate array comprising a plurality of core cells.
The core cells each include at least one P-type device and at least one N-type device arranged within the core cell in a predetermined layout or configuration.
The plurality of core cells is disposed in the array or chip in at least two groups.
One of the two groups is disposed in the chip so that the internal configuration of the core cells within that one group is the mirror image of the internal configuration of the core cells within the other one of the two groups.
The invention also comprises in such a CMOS gate array as described above a programmable word length memory.
The memory comprises an addressable memory array, a plurality of drivers and a data bus.
The plurality of drivers is coupled to the addressable memory and communicates with the memory array.
The data bus is comprised of a plurality of data bus lines of a predetermined number equal to or less than the number of the plurality of drivers.
The plurality of data bus lines is coupled to the plurality of drivers according to a predetermined metal mask mapping.
The data bus is configured according to the mapping to correspond to a related word length having a bit length equal to the number of data bus lines.
The memory as described above also includes a self-testing circuit.
This circuit is comprised of an address and data counter coupled to the memory for generating addresses of each location within said memory and for generating data for writing into each correspondingly addressed location.
A control circuit is coupled to the memory for controlling read/write cycles of the memory in response to addresses and data generated by the address and data counter.
An error detection circuit is coupled to the memory and to the address and data counter and compares data written into the memory (from the address and data counter under control of the control circuit) with data read from the memory in response to control by the control circuit

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