Hazard-free clocked master/slave flip-flop

DETAILED DESCRIPTION The present invention provides a clocked master/slave flip-flop comprising a master portion having plural similar logic elements for receiving at least data and clock inputs; each logic element providing an output to be associated in a manner dissimilar from the manner of logic association of the inputs; the result comprising the output of the master portion; a slave portion having plural similar logic elements for receiving as inputs the output of the master portion and clock inputs; each element providing an output to be associated in a manner dissimilar from the manner of logic association of the inputs to the slave portion to provide the true output of the flip-flop, and similar to the manner of logic association of the inputs to the slave portion to provide the complementary output of the flip-flop; the true and complementary outputs providing additional inputs to the elements of the master portion; a first redundant logic element operatively associated with the master portion; and a second redundant logic element operatively associated with the slave portion and with the first redundant logic element; the operative association providing both true and complementary outputs upon occurrence of clock skew.
From the foregoing it can be seen that it is a primary object of the present invention to provide an improved master/slave flip-flop.
It is another object of the present invention to eliminate timing hazards associated with skew of a clock pulse, particularly in systems embodying ECL LSI circuits.
It is a further object of the present invention to provide a fast, efficient, cost effective logic circuit of the master/slave flip-flop genus while eliminating problems associated with implementation of such by large scale integration techniques.
These and other objects of the present invention will become more apparent and better understood when taken in conjunction with the following description and drawings, wherein like characters indicate like parts and which drawings form a part of the present application