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Home I/O Systems High-density-microelectronic-packaging-module-for-high-speed-chips

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 High density microelectronic packaging module for high speed chips

Details
Inventors: Lindberg, Frank A.;
Assignee: Westinghouse Electric Corp. (Pittsburgh, PA)
Primary Examiner: Envall, Jr.; Roy N.
Assistant Examiner:
Attorney, Agent or Firm: Sutcliff; W. G.

A high density, multi-chip module applicable to VHSIC technology utilizing individually hermetically sealed microelectronic chip packages operable to be pretested, breadboarded and burned in prior to final module assembly. This microelectronic module comprises a multiplicity of interconnected chips in a high density fully heat sinked configuration, resulting in high clock speed and low power dissipation. This module further facilitates a short design cycle because no dedicated hard tooling is required. A packaging density is achieved which is about two and one-half times greater than the density achieved utilizing surface mounted leaded chip carriers with leads on 20 mil centers. This is because the packages are reduced in size after testing. This density increase results in a chip-to-chip line capacitance approximately half of conventional packaging due to the fact that the path lengths across the ceramic packages and across the P.C. board are reduced.

DETAILED DESCRIPTION In accordance with the above-stated requirements, the present invention, a high density microelectronic packaging method suitable for use in various module sizes including standard military formats, utilizes high density packaging, whereby 21/2 times greater packaging density is achieved compared to that of surface mounted leaded chip carriers.
The individual chip packages used for high density modules play a key role in the design fabrication and tests of this module.
We utilize in this invention miniature chip packages on a ceramic carrier.
These chip carriers have a conductive line fanout pattern which fans out first to a relatively close spacing such as a 10 mil center-to-center spacing, and then continues to fanout to a wider spacing such as a 20 mil center-to-center spacing.
These packaged chips are individually tested and interconnected to one another by a large wire wrapped panel.
This would enable the breadboard phase of the circuit to take place with the chips packaged in the same packages as the final configuration.
The breadboard panel could be used to burn the circuit in.
After tests and burn-in, the packages would be laser scribed from the back and snapped apart, removing the conductive lines that spread from the close spacing to the wider spacing.
The resulting small package would have closely spaced bonding pads for wire bonding to the next level of interconnect which would be a multi-layer interconnect structure such as a printed circuit board.
These chip packages are operable to be mounted, replaced and rebonded to the printed circuit board several times due to the oblong bonding pads on the printed circuit board.
And, the resulting module would have about half the chip-to-chip line capacitance as the same circuit would have if it were packaged with the 20 mil center leaded packages on a larger printed circuit board.
Most of the power would be dissipated on in the chips output buffers and the overall heat dissipation of the circuit would therefore be cut in half



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