Home | Links | Contact Us | More About Intellectual Property | Bookmark

Search patents:

Home

I/O Systems

High-frequency-selecting-switch-terminal

Data routing using status-response signals

The present invention provides an apparatus and method for routing data between multiple bus ...

Data and data strobe circuits and operating protocol for double data rate memories

What is claimed is: 1. A computer populated with a plurality of double data rate DRAMS including a ...

Non-volatile, electrically erasable and reprogrammable memory element

We claim: 1. A non-volatile, electrically erasable and reprogrammable memory element comprising a ...

High speed processing flip-flop

A high speed processing flip-flop contains a header circuit and a pulse flip-flop circuit. The ...

Compact multifunction logic circuit

The invention is a multifunction logic circuit, offering low power operation and compact layout....

Semiconductor storage device with redundancy arrangement

axi' An object of this invention is to shorten an access time in a semiconductor storage device ...

Broadband signal switching matrix network

An object of the present invention is to provide a broadband signal switching matrix network having ...

Programmable logic module and architecture for field programmable gate array device

OF A PREFERRED EMBODIMENT Those of ordinary skill in the art will realize that the following ...

Low-power, compact digital logic topology that facilitates large fan-in and high-speed circuit performance

In accordance with the present invention, there is provided a digital logic topology facilitating ...

Connector for flat cable

In accordance with this and other objects of the invention, there is provided a connector in which ...

High-frequency selecting switch terminal

Details

Inventors: Cheng, Yu Feng;
Assignee:
Primary Examiner: Albritton; C. L.
Assistant Examiner:
Attorney, Agent or Firm: Bacon & Thomas

An improved high frequency selecting switch terminal comprising two conductor pins which are coaxial. When a conductor pin from a cable is inserted into the terminal, it pushes the front end of the first conductor pin forward into the front end of the second conductor pin. At the front ends of the first and second conductor pins are first and second sliding blocks which force the pins forward. Thus, input signals are transmitted from the cable to the switch. The terminal further comprises a thick film resistor which connects the front end of the second conductor pin and a conductor ring which is disposed on the front surface of the second sliding block. When the cable is removed, the first and second sliding blocks move to the original position and the conductor ring contacts with the rim of the terminal housing. In this way, the terminal absorbs undesirable signals from the surroundings so as to prevent interference.

DETAILED DESCRIPTION OF THE INVENTION Referring to FIGS.
1 and 2, it can be seen that the housing (1) is threaded (11) on it's outer surface so as to engage with the high frequency selecting switch.
A fist ring rim (13) projects from the front end of the inner surface of the housing (1) and a second ring rim (14) projects from the middle of the inner surface of the housing (1) so as to divide the hollow space of the housing (1) into front and rear portions.
An insertion hole (12) is in the middle of the front surface of the housing (1) and an output hole (15) is in the middle of the rear surface of the housing (1).
A first sliding block (2) is disposed in the front portion of the housing (1) and contacts with the first ring rim (13).
The first sliding block (2) has a hole (24) at the center.
A first spring (4) is disposed between the first sliding block (2) and the second ring rim (14) so as to force the first sliding block (2) against the first ring rim (13).
A first conductor pin (21) is disposed in the front portion of the housing (1) and inserted through the first spring (4) and the hole (24) of the first sliding block (2).
The front end of the first conductor pin (21) forms a clamping member (211) which juts through the hole (24) of the first sliding block (2).
A second sliding block (3) is disposed in the rear portion of the housing (1) and has a hole (32) at its center.
A conductor ring (22) is disposed at the front surface of the second sliding block (3).
A spring (5) is disposed between the second sliding block (3) and the rear surface of the housing (1) so as to force the second sliding block (3) and the conductor ring (22) against the second ring rim (14).
A second conductor pin (31) is disposed in the rear portion and inserted through the second spring (5) and the hole (32) of the second sliding block (3).
Further, the front end of the conductor pin (31) forms a clamping member (311), which juts beyond the hole (32) of the second sliding block (3), and the rear end of the conductor pin (31) juts through the output hole (15) of the rear surface of the housing (1)

Related patents

	High speed pipeline merge sorter with run length tuning mechanism Accordingly, it is an object of the invention to provide a control data generator for a sort processor which requires no programs for generating the control data and is ...
	High speed pointer based first-in-first-out memory One embodiment of a high-speed pointer-based FIFO memory system constructed in accordance with this invention is depicted in FIG. 4. FIG. 4 is a block diagram showing ...
	Circuits, systems and methods for preventing queue overflow in data processing systems The principles of the present invention are preferably applied to circuits, systems, and methods for controlling the transfer of memory requests from an input queuing ...
	Polled FIFO flags It is desirable to provide a FIFO memory device which has polled status flags. It is also desirable to poll the FIFO memory device multiple times during its operation to ...
	Image forming system including interconnected and priority allocated image forming devices The object of the present invention is to provide an image forming system characterized in (1) having a network of a plurality of digital copying machines interconnected ...
	Method for allocating priorities to plurality of DMA engines for processing data packets based on bus phase and transactions status The present invention provides a method and apparatus for processing data packets through direct memory access (DMA) in transferring data packets between a bus and an ...
	Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system A method for transferring data between bus agents in a computer system including a system bus operating at a system bus clock rate is described. The method includes the ...
	Advanced programmable interrupt controller According to the present invention, a computer system includes an advanced programmable interrupt controller (APIC) in which an I/O APIC module is integrated in core ...
	Low speed serial bus protocol and circuitry OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, the computer system C according to the preferred embodiment is generally shown. The computer system C includes a ...
	Serial bus system for sending multiple frames of unique data Accordingly, the present invention discloses a computer system including a processor, a memory device, a North bridge logic coupling the processor and memory device, and ...

0.024
Archive: All patents - Links Copyright (c)2006 Eipa-patents.org - All rights reserved