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High-performance modular memory system with crossbar connections
| Details |
Inventors: Bauman, Mitchell A.;
Assignee: Unisys Corporation (Blue Bell, PA)
Primary Examiner: Kim; Matthew
Assistant Examiner: Bartaille; Pierre-Michel
Attorney, Agent or Firm: Atlass; Michael B., Johnson; Charles A., Starr; Mark T.
A modular, expandable, multi-port main memory system that includes multiple point-to-point switch interconnections and a highly-parallel data path structure that allows multiple memory operations to occur simultaneously. The main memory system includes an expandable number of modular Memory Storage Units, each of which are mapped to a portion of the total address space of the main memory system, and may be accessed simultaneously. Each of the Memory Storage Units includes a predetermined number of memory ports, and an expandable number of memory banks, wherein each of the memory banks may be accessed simultaneously. Each of the memory banks is also modular, and includes an expandable number of memory devices each having a selectable memory capacity. All of the memory devices in the system may be performing different memory read or write operations substantially simultaneously and in parallel. Multiple data paths within each of the Memory Storage Units allow data transfer operations to occur to each of the multiple memory ports in parallel. Simultaneously with the transfer operations occurring to the memory ports, unrelated data transfer operations may occur to multiple ones of the memory devices within all memory banks in parallel. The main memory system further incorporates independent storage devices and control logic to implement a directory-based coherency protocol. Thus the main memory system is adapted to providing the flexibility, bandpass, and memory coherency needed to support a high-speed multiprocessor environment. |
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DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS System Platform FIG.
1 is a block diagram of a Symmetrical Multi-Processor (SMP) System Platform according to a preferred embodiment of the present invention.
System Platform 100 includes one or more Memory Storage Units (MSUs) in dashed block 110 individually shown as MSU 110A, MSU 110B, MSU 110C and MSU 110D, and one or more Processing Modules (PODs) in dashed block 120 individually shown as POD 120A, POD 120B, POD 120C, and POD 120D.
Each unit in MSU 110 is interfaced to all PODs 120A, 120B, 120C, and 120D via a dedicated, point-to-point connection referred to as an MSU Interface (MI) in dashed block 130, individually shown as 130A through 130S.
For example, MI 130A.
interfaces POD 120A to MSU 110A, MI 130B interfaces POD 120A to MSU 110B, MI 130C interfaces POD 120A to MSU 110C, MI 130D interfaces POD 120A to MSU 110D, and so on.
In one embodiment of the present invention, MI 130 comprises separate bi-directional data and bi-directional address/command interconnections, and further includes unidirectional control lines that control the operation on the data and address/command interconnections (not individually shown).
The control lines run at system clock frequency (SYSCLK) while the data bus runs source synchronous at two times the system clock frequency (2.
times.
SYSCLK).
In a preferred embodiment of the present invention, the system clock frequency is 100 megahertz (MHZ).
Any POD 120 has direct access to data in any MSU 110 via one of MIs 130.
For example, MI 130A allows POD 120A direct access to MSU 110A and MI 130F allows POD 120B direct access to MSU 110B.
PODs 120 and MSUs 110 are discussed in further detail below.
System Platform 100 further comprises Input/Output (I/O) Modules in dashed block 140 individually shown as I/O Modules 140A through 140H, which provide the interface between various Input/Output devices and one of the PODs 120.
Each I/O Module 140 is connected to one of the PODs across a dedicated point-to-point connection called the MIO Interface in dashed block 150 individually shown as 150A through 150H
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I/O Systems 
