 Portable computer having latching hooks |
| In one embodiment, as shown in FIG. 1, computer system 10 includes a microprocessor 12, which is ... |
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| Data set network diagnostic system |
| FIG. 1 depicts a communication system, or network, in which the present invention is used. In ... |
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| Recording medium of flat surface with resin filled ring grove |
| Accordingly, a general object of the present invention is to provide a disc and a manufacturing ... |
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| Analog subscriber carrier system repeater with automatic gain and slope correction |
| OF THE INVENTION Referring now to FIG. 1 a subscriber carrier terminal at central office 2 is ... |
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| Plasma panel display selectively updatable on pel line basis |
| The system arrangement shown in FIG. 1 includes a processor 10 which may, typically, include a ... |
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| Display device |
| : It is an object of the present invention to provide a display control unit for performing optimal ... |
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| Multiport memory device |
| Accordingly, the object of the present invention is to provide a multiport memory device capable of ... |
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| Self-monitoring system |
| It is therefore an object of the present invention to provide a self-monitoring system capable of ... |
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| Architecture for a universal serial bus-based PC flash disk |
| OF THE INVENTION The present invention is of a flash memory device, containing one or more flash ... |
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High-speed multi-port FIFO buffer circuit
| Details |
Inventors: Denzel, Wolfgang E.; Engbersen, Antonius J.;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Olms; Douglas W.
Assistant Examiner: Blum; Russell W.
Attorney, Agent or Firm: Duffield; Edward H.
A buffer memory for use in the output queue of a packet switching network is described. The buffer consists of two separate memories (160, 170, 260, 270) connected through a multiplexer (310) to the output of the switch. A memory access control (120, 220) processes the incoming data which arrives on only some of the input lines (130, 230) and outputs it on adjacent output lines (140, 150, 240, 250). The data is written concurrently into consecutive memory locations in one of the two memories (160, 170, 260, 270). |
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DETAILED DESCRIPTION OF THE INVENTION FIG.
1 shows a data packet switch which consists of n input lines 5a-n, each of which is connected to a separate router 10a-n.
All of the routers 10a-n are connected to a single packet buffer memory 30 and each of the routers 10a-n are connected through lines 7a-n to one of a series of de-multiplexers 50a-n.
A memory 40 is used to store the addresses of unoccupied spaces within the packet buffer memory 30.
The memory 40 is connected through lines 42a-n and 46a-n to the routers 10a-n and through lines 42a-n and 44a-n to the de-multiplexers 50a-n.
Each of the de-multiplexers 50a-n is connected individually through lines 60 to each of a series of output queues 70a-n.
These output queues 70a-n are connected to multiplexers 20a-n through lines 72a-n and 76a-n and to the memory 40 through lines 72a-n and 74a-n.
All multiplexers 20a-n are connected to the data packet buffer memory 30 and output lines 25a-n.
In operation, the different packets arrive at some or all of the n inputs 5a-n and are then passed to the routers 10a-n.
Each packet consists of data and a header, in the latter of which amongst other things is an output address of the required one of the output lines 25a-n on which the packet is to be output.
The routers 10a-n place the contents of the incoming packet into the packet buffer memory 30 at an available free buffer address.
In principle it would be possible to save space in the packet buffer memory 30 by not storing in it the addresses of the output lines 25a-n to which the data packet is directed as this information is now redundant.
However, for reasons of simplicity, this information is not removed in the preferred embodiment and all of the header as well as the data is stored in the packet buffer memory 30.
Memory 40 stores the values of all the free (i.
e.
non-occupied) buffer addresses and supplies these to the routers 10a-n on demand along lines 42a- n and 46a-n.
The memory 40 is formed by any standard FIFO memory or by a memory similar to that used to form the output queues 70a-n
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I/O Systems 
