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Facsimile/telephone controller
OF THE INVENTION FIGS. 1a and 1b show a line sensing relay 14 and a double pole single throw latch relay 16 coupled between a telephone line 10 and a facsimile machine 1...
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High-frequency selecting switch terminal
OF THE INVENTION Referring to FIGS. 1 and 2, it can be seen that the housing (1) is threaded (11) on it's outer surface so as to engage with the high frequency ...
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High speed pipeline merge sorter with run length tuning mechanism
Accordingly, it is an object of the invention to provide a control data generator for a sort processor which requires no programs for generating the control data and is ...
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High speed pointer based first-in-first-out memory
One embodiment of a high-speed pointer-based FIFO memory system constructed in accordance with this invention is depicted in FIG. 4. FIG. 4 is a block diagram showing ...
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Circuits, systems and methods for preventing queue overflow in data processing systems
The principles of the present invention are preferably applied to circuits, systems, and methods for controlling the transfer of memory requests from an input queuing ...
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Polled FIFO flags
It is desirable to provide a FIFO memory device which has polled status flags. It is also desirable to poll the FIFO memory device multiple times during its operation to ...
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Image forming system including interconnected and priority allocated image forming devices
The object of the present invention is to provide an image forming system characterized in (1) having a network of a plurality of digital copying machines interconnected ...
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Method for allocating priorities to plurality of DMA engines for processing data packets based on bus phase and transactions status
The present invention provides a method and apparatus for processing data packets through direct memory access (DMA) in transferring data packets between a bus and an ...
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Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system
A method for transferring data between bus agents in a computer system including a system bus operating at a system bus clock rate is described. The method includes the ...
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Advanced programmable interrupt controller
According to the present invention, a computer system includes an advanced programmable interrupt controller (APIC) in which an I/O APIC module is integrated in core ...
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