Improved pointer FIFO controller for converting a standard RAM into a simulated dual FIFO by controlling the RAM's address inputs

DETAILED DESCRIPTION The invention provides a system which can manage the address inputs of a memory such that two independent FIFO buffers can be maintained or, alternatively, a receive FIFO may be implemented while a linked list is implemented for transmission of data.
In the preferred embodiment, the invention can support linked list transmission of two or more independent linked lists.
In one embodiment, the invention is comprised of a first means for storing a plurality of pointer addresses.
An output multiplexer is coupled to the first such means to select one of the pointer addresses for output to the address pins of the memory.
An incrementing circuit coupled to the output of the output multiplexer increments the selected pointer address and supplies it on a bus which is coupled into the inputs of the first means such that the selected pointer can be incremented for the next memory access.
In the preferred embodiment, the plurality of addresses are stored in a plurality of registers.
Each register has an input multiplexer for controlling which one of several inputs is selected for coupling into the data input of the register associated with the particular input multiplexer.
In one embodiment, there is a write address pointer register and a read address pointer register for a transmit FIFO and a write address pointer and a read address pointer for a receive FIFO.
In the preferred embodiment, one input of each input multiplexer is coupled to an initialization bus and another input of each multiplexer is coupled to the output of the incrementing circuit.
Thus, the particular pointer which is selected has its input multiplexer switched such that the output of the incrementing circuit is applied to the inputs of the selected pointer and the selected register output is coupled through the output multiplexer to the address pins of the memory.
Any other pointer storage register may then be accessed through the initialization bus and the appropriate input multiplexer such that the contents of that register may be initialized to any desired pointer address