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Information packet reception indicator for reducing the utilization of a host system processor unit
| Details |
Inventors: Williams, Robert A.; Tsai, Din-I; Kuo, Jerry C.;
Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA)
Primary Examiner: Lee; Thomas C.
Assistant Examiner: Du; Thuan
Attorney, Agent or Firm: Choi; Monica H.
A reception indicator is within a network peripheral that receives information packets for a host system from a communications network. The reception indicator of the present invention allows the network peripheral to operate in one of a plurality of modes. The reception indicator of the present invention asserts an interrupt signal at a respective optimum interrupt time for each of the modes. If the network peripheral is operating in a programmed I/O mode (i.e. a slave mode), a slave optimum interrupt time is determined. In this mode, a host processor unit within the host system reads portions of information packets from a readable data port in a host system interface. In this mode, an interrupt is asserted at the slave optimum interrupt time before a last byte of an information packet is expected to be received from the communications network. If the network peripheral is operating in a DMA (Direct Memory Access) mode, a DMA (Direct Memory Access) optimum interrupt time is determined. In this mode, the network peripheral automatically transfers the received information packet to a host memory of the host system. In this mode, an interrupt signal is asserted at the DMA optimum interrupt time before a last byte of an information packet is expected to be copied to the host memory. In this manner, the present invention allows the network peripheral and the host system to operate in one of the modes that is most efficient for data processing while at the same time issuing an interrupt at a respective optimum interrupt time for each of the modes. |
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DETAILED DESCRIPTION The present invention enables a reception related interrupt to be issued by a network peripheral at a time that reduces the utilization of a host system's processor unit and overlaps the reception of an incoming information packet with the host system's interrupt latency.
In embodiments of the present invention, a network peripheral issues a reception related interrupt early enough before the end of an incoming packet to enable a processor unit to begin processing the packet before the packet is fully received.
The network peripheral also provides the reception interrupt, so that the time the processor sits idle in an interrupt service routine is reduced.
In determining when to issue the reception interrupt, the network peripheral determines a length value for the incoming packet and employs the length value along with other parameters to determine the time for issuing the reception interrupt.
The length value may be determined by the network peripheral based on information in the incoming information packet.
Furthermore, the network peripheral may adjust the parameters based on the processing load of the host system's processor unit.
Embodiments of the present invention provide for a network peripheral that is capable of issuing a single interrupt to a host processor to signal that an incoming information packet requires processing.
Such an interrupt is issued so that interrupt latency of the host system and processing of the incoming information packet are overlapped with the reception of the incoming packet.
Further, network peripherals in accordance with the present invention are able to provide such an interrupt for information packets that conform to a plurality of user specified network operating system protocols.
As a result, it is significantly less likely that the processor unit will remain idle during the execution of an interrupt service routine for processing the reception of the incoming information packet.
Embodiments of the present invention include a reception indicator within a network peripheral that receives information packets for a host system from a communications network
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