Information processing system

DETAILED DESCRIPTION OF EMBODIMENTS Several examples of preferred embodiments of the present invention will be explained in details with reference to the drawings in the followings.
FIG.
2 is a general overview of an information processing system in accordance with a first embodiment of the present invention.
FIG.
3 is a schematic diagram for illustrating the major constituent elements of the information processing system in accordance with the present invention.
Also, FIG.
4 is a flowchart showing the procedure of performing debugging for the information processing system as illustrated in FIG.
3.
In FIG.
2, the information processing system in accordance with the present invention is composed of a microcomputer 10 comprising a CPU 1, an on-chip debug circuit 2, a security circuit 3, a control circuit 4, a ROM 11 and other necessary peripheral circuits 12'.
Also, the microcomputer 10 can be connected to a host computer through an on-chip debug ICE 12 in order to conduct debug operation.
The security circuit 3 is composed of a logic sum (OR) gate 5 receiving a power-on reset signal for resetting the microcomputer at power up and a security bit signal, a logic product (AND) gate 6 receiving the inversion of the security bit signal and a debug enabling signal for enabling the reset operation of the security bit signal and a register (RS flip-flop) 7 for receiving the output of the logic OR gate 5 as a SET input signal (S) and the output of the AND gate circuit 6 as a RESET input signal (R) and outputting a security signal as an output signal Q.
The debug enabling signal is output from a gate 3b connected to a security clear register 3a as a user I/O register and becomes active only when a predetermined enable code is loaded to the security clear register.
The security clear register can be set or reset by executing input/output instructions of the CPU 1.
The security bit is one bit of an input/output register, referred to as a security register 3c, which can be set or reset by executing input/output instructions of the CPU 1