Integratable, bus-oriented transmission system

DETAILED DESCRIPTION It is an object of the invention to increase the switching speed given a data transmission system of the type initially defined and to avoid the disadvantages of a high surface requirement and power consumption.
This object is achieved by providing a clock generator means for generating first and second phase shifted clock signals having non-overlapping activation levels.
A first precharging means is provided for precharging the address bus in accordance with the activation level of the first clock signal.
A second precharging means is provided for precharging the data bus in accordance with the activation level of the first clock signal.
Means are provided for addressing the register means in accordance with the activation level of the second clock signal.
The at least one address source means charges the address bus with an address signal in a time between the activation levels of the first and second clock signals.
The invention has the advantage that both control lines or the address bus as well as the data bus are prechargeable in a two-phase clock system.
The charging thus ensues during a non-critical time phase.
It is further assured that no danger of overlap of address signals that are generated by a plurality of address sources exists within the transmission system.
The transient response behavior of the control line is taken into consideration by the control loop so that multiple addressing is impossible.