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Integrated circuit I/O pad cell modeling
| Details |
Inventors: Peters, Michael J.; Collins, Richard L.; Musolf, David M.; Bashford, Patrick R.; Wright, Bradley J.;
Assignee: Hynix Semiconductor, Inc. (Seoul, KR)
Primary Examiner: Louis-Jacques; Jacques H.
Assistant Examiner:
Attorney, Agent or Firm: Townsend and Townsend and Crew LLP
A design system for modeling bi-directional pad cells, the interaction of internal pull cells/resistors with pad cells of all types, and the interaction of external pull cells/resistors with pad cells of all types. This modeling technique involves the use of three separate pins on each bi-directional pad cell: an input-only pin, an output-only pin, and a resolved pin. The input-only pin reflects the data that is supplied to the pad from external sources. The output-only pin reflects the data that is supplied as output from the pad cell (strong data from the output driver). The resolved pin reflects the combination of the input and the output data that are present, as well as the effect of resistive data supplied by pull-up/down resistors/cells. The output-only and resolved pins are implemented as internal or hidden pins within a pad cell model. These pins are included in the model for the I/O pad cells in a given library. The existing pad pin serves as the input-only pin. The model provides two modes of operation such that the same model can be used for either chip-level or system-level simulations. |
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DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT In the design of integrated circuits, including application specific integrated circuits (ASICs), there are numerous types of design test tools available to assist the logic designer in logic entry, simulation, layout, test pattern generation, etc.
These tools are well known in the art.
The present invention is a model used to represent a particular portion of an integrated circuit design, specifically the I/O pad cell.
This model is used in conjunction with a simulator to synthesize the behavior of an actual I/O pad cell when embodied as part of a resulting integrated circuit.
FIG.
10, including FIGS.
10A-C, shows a typical design methodology for designing integrated circuits, and in particular for designing ASICs.
First, initial planning of the design is done at 90.
The design is then entered at 91 using standard CAE/CAD tools known in the industry, such as those from Cadence Design Systems, Mentor Graphics, Synopsis and Viewlogic.
Part of logic entry includes compiling the pad cells, using an I/O compiler such as the VS500 I/O Compiler, available from AT&T Global Information Solutions Company, Microelectronics Division located in Ft.
Collins, Colo.
(hereinafter AT&T MPD).
After design entry, the user can optionally perform static timing analysis at 92 (using a tool such as VeriTime, available from Cadence Design Systems, Inc.
which is located in San Jose, Calif.
), as well as generate input stimulus waveforms at 93 for use in subsequent simulation (using a tool such as Wisil, also available from AT&T MPD).
After such stimulus waveform creation, the user can optionally perform functional simulations at 94.
The user then performs real time simulation at 95 using the same simulator.
These simulation steps are where the present invention is utilized.
The particular model detailed herein was written for use with the Verilog simulator, such simulator being available from Cadence Design Systems.
After simulation, power analysis can optionally be performed at 96 using a PowerCalc tool, available from AT&T MPD
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I/O Systems 
