Integrated circuit in complementary circuit technology comprising a substrate bias generator

DETAILED DESCRIPTION We claim: 1.
In an integrated circuit executed in complementary circuit technology comprising a pair of field effect transistors (T1, T2) of different channel types, said first field effect transistor (T1) being provided in a doped semiconductor substrate (1) of a first conductivity type and at least one second field effect transistor (T2) being arranged in a well-shaped semiconductor zone (2) of a second conductivity type provided in said semiconductor substrate (1), said semiconductor zone adapted to be wired to a supply voltage (V.
sub.
DD), whereby a terminal region (3) of at least one first field effect transistor (T1) is charged with a grounded potential (VSS), the semiconductor substrate adapted to be connected to the output (17) of a substrate bias generator (16) to which the grounded potential and the supply voltage are supplied and which biases the p-n junction between the terminal region (3) of the first field effect transistor lying at ground potential and the semiconductor substrate (1) in non-conducting direction, the combination comprising; an electronic switch for connecting the output (17) of the substrate bias generator (16) to ground potential for a predetermined time after said supply voltage (V.
sub.
DD) is applied; and a time delay circuit connected between said electronic switch and said supply voltage (V.
sub.
DD) for opening said switch in response to said supply voltage after said predetermined time.
2.
The integrated circuit according to claim 1, wherein said substrate bias generator (16) is integrated with said field effect transistor on the same semiconductor substrate (1).
3.
The integrated circuit according to claim 1 or 2, including means for connecting the output (17) of said substrate bias generator (16) to a first semiconductor region (20) of the second conductivity type inserted into the semiconductor substrate; a second semiconductor region (21) of the second conductivity type inserted into the semiconductor substrate and connected to ground potentiaI; and a region of the semiconductor substrate (1) lying between these two semiconductor regions (20, 21) being covered by a gate (22) separated from the boundary surface (1a) of the semiconductor substrate by a thin, electrically insulating layer (23), whereby said gate, together with the two semiconductor regions, forms a first field effect switching transistor which constitutes said electronic switch (S1)