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| Panel assembly for compact PCI system interface card |
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| Sub-card board connector, sub-card board, modem sub-card, and a computer having this connector |
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| Compact PCI connector guide |
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| Portable data collection |
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| First-in, first-out (FIFO) buffer |
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Integrated test circuit
| Details |
Inventors: Whetsel, Jr., Lee D.;
Assignee: Texas Instruments Incorporated (Dallas, TX)
Primary Examiner: Moise; Emmanuel L.
Assistant Examiner:
Attorney, Agent or Firm: Bassuk; Lawrence J., Brady; W. James, Telecky, Jr.; Frederick J.
A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously. |
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DETAILED DESCRIPTION In accordance with the present invention, a boundary scan test system is provided which substantially eliminates the disadvantages and problems associated with prior testing systems.
The boundary scan test system of the present invention comprises a first multiplexer connecting a plurality of inputs to a first memory, responsive to control signals provided by a control bus.
The output of the first memory is connected to a second memory.
The output of the second memory is connected to an input to a second multiplexer along with one or more other inputs.
The second multiplexer is controlled by another control signal on the control bus.
The output of the first memory and the output of second memory are connected to the first multiplexer as inputs.
The present invention provides a variety of functions for testing purposes.
The test cell is operable to both reserve data inputs and control data outputs to and from the cell.
The test cell may operate in two modes: "normal" mode and "testing" mode.
In normal mode, the test cell provides a data path through which inputs and outputs may propagate freely through the test cell.
While in the normal mode, the test cell can also load and shift test data, remain in an idle state, or toggle test data without disturbing the normal operation of the integrated circuit.
Further, while in normal mode, a predetermined test data bit may be inserted into the data stream.
Also, the test cell may perform a self-test while in the normal mode to insure correct operation of the test cell.
In the test mode, the test cell inhibits the normal flow of data through the test cell.
Normally, the test cells in the integrated circuit will have been prepared to output an initial test pattern.
While in the test mode, the test cell may perform Idle, Load, Shift, and Toggle operations.
The present invention provides significant advantages over the prior art.
First, the test cell of the present invention may be used to perform internal and external boundary testing simultaneously, in order to reduce overall test time
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I/O Systems 
