Internally cached static random access memory architecture

DETAILED DESCRIPTION The present invention, in its broadest form, is directed to a circuit for internally caching a memory device having a main memory.
The circuit is comprised of a cache memory of smaller size than the main memory for storing certain portions of the same data stored in the main memory.
A tag memory is provided for mapping the information stored in the cache memory.
A logic circuit is in communication with the main memory, the cache memory, and the tag memory for controlling the input of data thereto and output of data therefrom.
The cache memory, tag memory, and logic circuit are carried internally in the memory device.
The present invention solves the problem of improving the performance of SRAMs by providing an internally cached SRAM circuit comprised of a main static random access memory array for storing data.
A cache static random access memory array of smaller size than the main array is provided for storing certain of the same data that is stored in the main memory.
A tag static random access memory array for mapping the information stored in the cache memory is also provided.
A logic circuit is in communication with the main memory, the cache memory, and the tag memory for interrogating the tag memory in response to a request for data.
The logic circuit retrieves the requested data from either the main memory or the cache memory in response to the results of the interrogation.
The logic circuit also inputs the retrieved data to the cache memory while updating the tag memory if the retrieved data is found only in the main memory.
Finally, the logic circuit inputs data to both the main memory and the cache memory while updating the tag memory in the event new data is to be stored.
The foregoing cached memory device results in an SRAM with improved performance because the smaller cache memory can respond more quickly than the larger main memory, even though both memory arrays are constructed of static cells.
That is because, among other factors, a smaller SRAM has less internal capacitance to overcome and therefore can be read more quickly