Logic cell which can be configured as a latch without static one's problem

DETAILED DESCRIPTION According to the present invention, a logic cell is provided in which sequential functions may be generated.
Under control of a clock signal, an output signal can be fed back as input and thereby latched into the feedback path, or a data signal can be forwarded to the output and not latched.
The latch includes an input section which receives a data input signal and a feedback section.
When the cell is in a latching mode, the circuit feeds back the output signal.
To switch between the transparent mode in which an input data signal is forwarded to the output terminal and the latching mode in which the output signal is fed back as an input signal, a clock signal enables one section and disables the other.
Depending upon the particular transistors used to implement the gates of the cell, a transition of a latch enable signal from the transparent mode to the latched mode may cause a logical zero to be latched when a logical one was present on the data input line.
This is called the static ones hazard and occurs because a switching latch enable signal can cause a logical 0 signal to appear at the output of the data input section before the logical 1 data has been captured into the feedback section.
Thus a logical 0 is erroneously captured.
Such an error must be avoided of course.
In accordance with the invention, this static ones hazard is avoided by controlling trip points in the gates of the cell so that the cell implements a make-before-break transition.
A trip point may be defined for an inverter as that voltage at which the input voltage is equal to the output voltage.
If the inverters have relatively low trip points and logic gates have relatively high trip points, a static ones' error is found to occur.
If the inverters have a higher trip point and the logic gates have a lower trip point, the Q output signal is found to properly follow the D input signal through the positive and negative shifts of the clock signal.
By manufacturing inverters at the cell input to have higher trip points than trip points of the logic gates which forward the input data or the feedback data, the static one's problem is avoided