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Low-noise frequency divider
| Details |
Inventors: Canard, David; Fillatre, Vincent;
Assignee: U.S. Philips Corporation (New York, NY)
Primary Examiner: Lam; Tuan T.
Assistant Examiner:
Attorney, Agent or Firm: Biren; Steven R.
A frequency divider DIV/4 composed of memory cells (DL1 . . . DL4) realized in ECL technology, whose data paths constitute a loop, the data output Q4 of the last memory cell DL4 being cross-connected to the data input D1 of the first memory cell DL1. The clock inputs Ck of the memory cells DL1, DL3 of the odd rank are connected to the input IN of the frequency divider circuit DIV/4, while the others are cross-connected to said input. Such a frequency divider generates a noise having a unique frequency which is twice the frequency of the input signal, irrespective of the division ratio obtained. |
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DETAILED DESCRIPTION It is an object of the invention to remedy these drawbacks to a great extent by proposing a frequency divider which generates a single parasitic signal having a unique frequency irrespective of the division ratio between its input signal and its output signal, while said ratio can be chosen as an arbitrary multiple of two.
To this end, an integrated circuit comprising a frequency divider according to the invention is characterized in that the frequency divider comprises 2.
N memory cells of the above-mentioned type, the data output of the i.
sup.
th memory cell, referred to as memory cell of rank i, being connected, for i=1 to 2.
N-1, to the data input of the memory cell of rank i+1, the data output of the memory cell of rank 2.
N being cross-connected to the data input of the memory cell of rank 1, the data output of one of the memory cells constituting the output of the frequency divider circuit, the clock input of each memory cell of an odd rank being connected to the input of the frequency divider circuit, the clock input of each memory cell of an even rank being cross-connected to said input.
All of the memory cells included in such a frequency divider receive the same input signal or its inverse value.
Consequently, the noise generated in the power supply terminals only has a single harmonic whose frequency is twice the frequency of the input signal of the frequency divider, irrespective of the division ratio obtained with the aid thereof.
Such a frequency divider thus constitutes a filter for parasitic signals which enables only a single harmonic to be generated.
Moreover, it allows a division of the value of the input frequency by an arbitrary even number.
However, a division ratio of the value of 2.
N involves the use of 2.
N memory cells.
In comparison with a structure composed of known cascade-arranged two-to-one dividers, a frequency divider according to the invention is thus less economical in terms of silicon surface required for its realization, as soon as 2
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I/O Systems 
