Low-power, compact digital logic topology that facilitates large fan-in and high-speed circuit performance

DETAILED DESCRIPTION In accordance with the present invention, there is provided a digital logic topology facilitating large fan-in, high-speed and low-power consumption.
The topology utilizes a Domino logic structure that is composed of dynamic, or clocked, gates coupled with static gates.
In the present invention, the dynamic gate is preferably a dynamically precharged gate (DPG).
The static gate is a Pseudo-NMOS gate, and preferably an improved Pseudo-NMOS gate designed to minimize power consumption, have equivalent output rise and fall times, and have reduced output offset voltage.
The coupling of DPG and improved Pseudo-NMOS gates facilitates a high-speed, low-power implementation of combinational logic functions having many inputs and sum terms.
The DPGs are dynamic and consume no static power.
The Pseudo-NMOS gates, improved or traditional, consume significantly more power than DPGs or CMOS gates.
However, the Pseudo-NMOS gates are typically used in the second stage of the NOR-NOR structure.
The number of DPGs typically is five to ten times the number of Pseudo-NMOS gates.
Therefore because the power consumed by the Pseudo-NMOS gates is averaged over the large fan-in logic circuit, the power consumption of a DPG-Pseudo-NMOS gate with large fan-in is significantly less than a large fan-in circuit using purely Pseudo-NMOS gates.
As a result, complex combinational logic functions having many inputs, but relatively few sum terms, can be implemented with a DPG-Pseudo-NMOS structure having low power consumption.
Improved Pseudo-NMOS gates can be implemented to reduce the power consumption.
The improved gates utilize clock and other signals to minimize power consumption of the gate when the clock or gate output are low.
The improved Pseudo-NMOS gates can also be used to implement new latch gates having logic functionality.
Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings