Main storage access priority control system that checks bus conflict condition and logical storage busy condition at different clock cycles

DETAILED DESCRIPTION It is an object of the present invention to provide an improved access priority control system for a main storage for a computer in which the delay time in a priority cycle is reduced, and the time for one clock cycle is reduced.
It is another object of the present invention to reduce the amount of hardware needed for an access priority control system for a main storage for a computer.
According to the present invention, there is provided an access priority, control system for a main storage for a computer, for controlling a signal transmission to the main storage when a plurality of storage access requests are output from at least one processor related to the main storage, in which the system includes a first access request port unit for holding, at least temporarily, a segment address of the storage access requests from the processor; a first control unit responsive to the output of the first access request port unit for checking a bus conflict condition and prohibition condition of a destination storage segment determined by the address of the storage access request; a second access request port unit responsive to the output of the first control unit for holding at least temporarily an intra-segment address of the storage access request; and a second control unit responsive to the output of the second access request port unit for checking a logical storage busy condition in the storage segments.