 Re-configurable block length cache |
| The invention concerns a cache having a cache memory for storing a plurality of data words, such as,... |
|
| Detecting the presence of a device on a computer system bus by altering the bus termination |
| It is simple to detect when an ISA board drives values onto the data bus different from the bus' ... |
|
| Conversion of multilevel digital data to binary data |
| The above-described disadvantages of the prior art are overcome with the present invention and an ... |
|
| Data storage buffer system and method |
| The problems with the methodologies discussed above have been alleviated by the present invention. I... |
|
| Binary input processing in a computer using a stack |
| With reference now to the drawing, it may be seen that the various blocks depicted therein are ... |
|
| Circuit for designating instruction pointers for use by a processor decoder |
| FIG. 2 schematically illustrates an instruction pointer designation circuit 200 in accordance with ... |
|
| Methods and apparatus for translating incompatible bus transactions |
| Circuit arrangements and methods are disclosed for upgrading an 040-based personal computer system ... |
|
| Data-array processing system wherein parallel processors access to the memory system is optimized |
| OF THE PREFERRED EMBODIMENTS Preferred embodiments of the invention will now be described, by way ... |
|
|
Master-target based arbitration priority
| Details |
Inventors: Tavallaei, Siamak; Kotzur, Gary B.;
Assignee: Compaq Computer Corporation (Houston, TX)
Primary Examiner: Sheikh; Ayaz R.
Assistant Examiner: Thlang; Eric S.
Attorney, Agent or Firm: Harris; Jonathan M., Heim; Michael F. Conley, Rose & Tayon, P.C.
A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and/or keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The SMC includes logic to monitor PCI cycles and to issue error signals in the event of a system error. The SMC also isolates failed components by masking request, grant and interrupt lines for the failed device. Further, if a spare component is provided, the SMC permits dynamic switching to the spare. In addition to detecting errors and performing survival and maintenance operations, the SMC enhances system performance during normal operations by supporting master-target priority determinations to more efficiently arbitrate mastership of system busses such as the PCI bus. |
|
DETAILED DESCRIPTION The problems outlined above are in large part solved by a remote communication system of the present invention.
The remote communication system includes a system management module (SMM) which can be included in the server system (such as, for example, by connection to an expansion bus on the server system board).
Preferably, the SMM is connected to the PCI bus, although the SMM may be located elsewhere if desired.
The SMM includes a system management processor (SMP) and a system management central (SMC) control logic.
The SMP and SMC connect to a system management (SM) local bus, which also connects to a VGA controller and a keyboard interface controller.
The inclusion of a VGA controller on the SM local bus permits an administrator or other user to remotely monitor video data reflecting the operation of the SMM.
Similarly, the inclusion of the keyboard interface on the SM local bus permits the system administrator or other user to directly access the components on the SMM (such as the SMP and SMC) by generating commands remotely for these components.
The implementation of the VGA controller and the keyboard interface as part of the SMM thus permits an administrator to gather information stored by the SMM and to command the SMM to perform certain operations.
In addition, the inclusion of these components in the SMM permits a user to access the server in a virtual terminal mode from a remote location.
The SMC of the present invention preferably includes a bus arbitration and monitor unit that preferably operates as the main arbitration unit for the PCI bus.
Thus, all requests for mastership of the PCI bus pass through the SMM.
The bus arbitration and monitor logic receives bus mastership requests from the various bus masters in the system and grants mastership based upon certain criteria.
In addition, the arbitration and monitor logic monitors the activities of the bus master to determine if the bus master responds adequately to mastership grants.
In the absence of a proper response, the arbitration and monitor logic will again attempt to grant bus mastership to the designated bus master
|
| Related patents |
|
|
Single chip remote access processor
The single chip integrated remote access processor of the present invention has a plurality of communication interface units, including a local area network (LAN) ...
|
|
|
Method and system for supporting non-deterministic burst lengths in a memory system employing extended data out(EDO)DRAM
The problems outlined above are in large part solved by a computer memory system in accordance with the present invention. Broadly speaking, the present invention ...
|
|
|
Method and system for dynamically assigning addresses to an input/output device
OF THE PREFERRED EMBODIMENTS In the following description, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of ...
|
|
|
Unstable data recognition circuit for dual threshold synchronous data
The present invention is a circuit that allows digital data acquisition instruments to recognize when dual threshold synchronous data being monitored is unstable. Each ...
|
|
|
Automatic pin circuitry shutoff for an integrated circuit
In accordance with the preferred embodiment of the present invention, a method and circuitry is provided which allow for the prevention of tester induced failures and ...
|
|
|
Input level detection circuit
According to one aspect of the present invention, an apparatus for activating a logic device when the logic device is required to perform an operation is provided. The ...
|
|
|
Stack caching method with overflow/underflow control using pointers
Accordingly, the present invention provides a stack management unit including a stack cache to accelerate data retrieval from a stack and data storage into the stack. In ...
|
|
|
Image recording device
It is a principal object of the present invention to provide an image recording device capable of contiguously recording a plurality of images based on image signals, ...
|
|
|
Image recording apparatus having a small-capacity frame memory and an image recording method
Accordingly, it is a primary object of the present invention to provide an image recording method capable of reducing the capacity of a frame memory and of recording ...
|
|
|
Method and apparatus for unwinding image data
The present invention solves the above problems by providing a method and apparatus for reformatting (or unwinding) graphics images in a bit map memory from a row-...
|
|
|
I/O Systems 
