Memory access address comparison

DETAILED DESCRIPTION It is an aim of embodiments of the present invention to provide write protection circuitry which addresses the problems of the prior art.
According to one aspect of the present invention, there is provided a memory system comprising a memory array having a plurality of memory locations; a plurality of write ports for writing to said memory array; write protection circuitry for preventing more than one memory location from being addressed at the same time in a write operation, said write protection circuitry providing write enable signal for each write port, said write enable signals being applied to said memory array; and circuitry for controlling the timing of the application of the write enable signals to said memory array, said circuitry for controlling said timing being upstream of said write protection circuitry.
As a circuitry for controlling the timing of the application of the write enable signals is upstream of the write protection circuitry, there would be no effect on the performance of the memory system if write protection is not required.
By providing the write protection before the latches as in the prior art, unnecessary delays occur even when write protection is not needed.
This loss of timing is prevented by embodiments of the invention where the write protection is downstream of the latches.
It is preferred that the output of the write protection circuitry be directly applied to the memory array.
Putting the write protection circuitry as the last stage before the memory array protects the circuit from any transitory state at the outputs of the latches.
Since it is the ultimate combination of the write enable signals which controls the writing operation, the protection is effective.
The write protection circuitry may be arranged to assign a hierarchy to said write ports.
For example, n write ports may be provided and the first write port may have priority over the remaining n-1 ports and the nth port may have the lowest priority.
The write enable signals output by the write protection circuitry may be low when active and high when disabled