Memory cell with separate read and write paths and clamping transistors

DETAILED DESCRIPTION What is claimed is: 1.
A random access memory circuit of the type having a plurality of memory cells and a main word line for providing a variable voltage which selectively enables data to be written into and read from the cells, each memory cell comprising: a pair of cross-coupled bipolar transistors wherein the base of a first transistor of said pair is connected to the collector of the second transistor of said pair and the collector of said first transistor is connected to the base of said second transistor; a pair of load resistors respectively connecting the collectors of said pair of cross-coupled transistors to a bias voltage; a pair of clamping transistors responsive to the voltage on said word line for respective controlling voltage levels at the collectors of said pair of cross-coupled transistors, said clamping transistors respectively connecting the collectors of said pair of cross-coupled transistors to a first pair of bit lines which conduct currents that are sensed to determine the value of data stored in the cell; and means for connecting emitters of said pair of cross coupled transistors to a second pair of bit lines.
2.
The memory circuit of claim 1 wherein each of said clamping transistors has a base connected to said word line, an emitter connected to the collector of an associated one of said pair of cross-coupled transistors, and a collector connected to a respective one of the bit lines in said first pair of bit lines.
3.
The memory circuit of claim 1 wherein said bias voltage is the voltage on said word line.
4.
The memory circuit of claim 1 further including an auxiliary word line providing a voltage related to the voltage on said main word line, and wherein said clamping transistors in each memory cell have base electrodes connected to said main word line, and said load resistors are connected to said auxiliary word line.
5.
The memory circuit of claim 1 comprising plural word lines, and wherein said load resistors of each cell are connected to one of said plural word lines and the base electrodes of said pair of clamping transistors of each cell are connected to a different one of said plural word lines, said plural word lines providing respective voltages which are related to one another