 Elasticity buffer for data/clock synchronization |
| OF PREFERRED EMBODIMENT The present invention has application to any data transfer system that ... |
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| Computer systems and methods for pipelined transfer of data between modules |
| Synchronous Global Bus The chief object of the present invention is to perform fast block transfers ... |
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| Dynamic random access memory system |
| It is object of the present invention to minimize the number of address control pins and signal ... |
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| Optical clock distribution system |
| OF THE PREFERRED EMBODIMENT In the following detailed description of the preferred embodiment, ... |
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| Modular bus with single or double parallel termination |
| Single Channel Bus In one embodiment of a modular single channel bus architecture, a master bus ... |
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| Memory controller with low skew control signal |
| OF THE PREFERRED EMBODIMENTS Prior to discussing the preferred embodiments of the invention, a ... |
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| Backup method and apparatus allowing only replaced data to be transferred |
| This invention aims at enhancing efficiency in utilizing a communications link by shortening a data ... |
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| Integratable, bus-oriented transmission system |
| It is an object of the invention to increase the switching speed given a data transmission system ... |
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| Discharge circuit for a semiconductor memory including address transition detectors |
| Therefore, a main object of the present invention is to provide a semiconductor memory device which ... |
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Memory device with multiple internal banks and staggered command execution
| Details |
Inventors: Ryan, Kevin J.; Wright, Jeffrey P.;
Assignee: Micron Technology, Inc. (Boise, ID)
Primary Examiner: Popek; Joseph A.
Assistant Examiner:
Attorney, Agent or Firm: Seed and Berry LLP
In a memory device such as a page-oriented synchronous dynamic random access memory device (SDRAM), a memory array and associated circuitry are divided into multiple internally defined circuit banks. Commands and addresses applied to the memory device affect all internal banks identically, but on a time-staggered basis. In an eight bank embodiment, activation of a selected row is first initiated in Bank0 by registration of an ACTIVE command and a coincident row address. One system clock cycle later, activation of the selected row is initiated in Bank1, and so on until activation of the selected row is initiated in Bank7 seven clock cycles after the initial registration of the command. A READ or WRITE command and coincident column address can be applied after the activation time limit has been met for the selected row in Bank0. The READ or WRITE command then affects successive banks in the above-described time staggered manner. Similarly, a PRECHARGE command can be applied when the read latency or write recovery time limit has been met for Bank0, and this command is executed in a time staggered manner in the successive banks. In a four bank embodiment, command registration and execution is staggered every two successive system clock cycles. |
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DETAILED DESCRIPTION According to the present invention, a memory device has an array of memory cells arranged in a plurality of subarrays, with each subarray having the memory cells arranged in rows and columns.
Commands applied to the memory device affect all subarrays identically, but on a time-staggered basis provided for internal to the memory device.
Command execution is initiated in a first of the subarrays, and a predetermined time later in a second of the subarrays, and so on until command execution is initiated in a last of the subarrays.
After completed execution of a command in the first subarray, a subsequent command in a data transfer operation can be applied to the memory device, before completed execution of earlier commands in other subarrays.
Thus, data transfer operations to and from the memory device can be executed continuously.
The memory device includes a plurality of control circuits, each coupled to a corresponding one of the subarrays.
Each control circuit selects in the corresponding subarray a first memory cell identified by a row and column address provided on an address bus.
The first memory cell in a first of the subarrays is selected at a first time, and the first memory cell in each of other subarrays is selected after a respective time interval (which may be an integer multiple of system clock cycle periods) following the first time, until the first memory cell in a last of the subarrays has been selected.
Data is transferred between a data bus and the first memory cell in the first of the subarrays at a second time, and data is transferred between the data bus and the first memory cell in each of the other subarrays after the respective time interval following the second time.
Each control circuit also selects in the corresponding subarray a second memory cell identified by a second combined row and column address provided on the address bus.
The second memory cell in the first of the subarrays is selected at a third time, and the second memory cell in each of the other subarrays is selected after the respective time interval following the third time
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I/O Systems 
