Memory device with programmable self-refreshing and testing methods therefore

DETAILED DESCRIPTION We claim: 1.
A programmable refresh circuit integrated with a semiconductor memory device having a memory array accessed through word lines and bit lines, said programmable refresh circuit comprising: a self-timed oscillator that outputs a clocking signal; programmable pattern generating means for generating a first signal pattern; counter means connected to receive the clocking signal output from the self-timed oscillator and the first signal pattern generated by the programmable pattern generating means, said counter means having a count driven by said clocking signal and outputting a signal pulse upon the count reaching a digital pattern representation corresponding to the first signal pattern generated by said programmable pattern generating means; and refresh control logic connected to said counter means for receiving the signal pulse output therefrom, said refresh control logic responding thereto by refreshing a portion of the memory array of the semiconductor memory device, wherein output of multiple signal pulses from the counter means defines a refresh rate at which the memory array is refreshed, said refresh control logic further including means for disabling refreshing of the memory array for a programmable "wait state interval" subsequent to said refresh control logic receiving from a control system connected to the semiconductor memory device a signal initiating self-refresh, and means for enabling refreshing of the memory array subsequent to said wait state interval.
2.
The programmable refresh circuit of claim 1, wherein the semiconductor device receives a row address strobe (RAS) signal and a column address strobe (CAS) signal from the control system connected thereto, and wherein the signal initiating self-refresh comprises a CAS before RAS transition of signals received from the control systems.
3.
The programmable refresh circuit of claim 1, wherein the programmable pattern generating means includes means for generating a second signal pattern, and wherein said refresh control logic is connected to receive the second signal pattern generated by the programmable pattern generating means, and wherein the refresh control logic includes comparing means for comparing a portion of the digital pattern representation of the count of the counter means with the second signal pattern generated by the programmable pattern generating means to determine the wait state interval subsequent to initiation of refresh