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Details
Inventors: Neal, Joseph H.; Poteet, Kenneth A.;
Assignee: Texas Instruments Incorporated (Dallas, TX)
Primary Examiner: Gossage; Glenn
Assistant Examiner:
Attorney, Agent or Firm: Donaldson; Richard L., Bassuk; Lawrence J., Havill; Richard B.

A semiconductor memory architecture, which includes a given number of discrete components, provides a memory module of increased capacity. The memory module includes a plurality of discrete data memory circuits each organized to provide an individual data string having a length that is an integer multiple of four bits. The data memory circuits are arranged to provide a combined data string having a length equal to the sum of the individual data string lengths. Each data memory circuit includes a signal line connected to control transfer of individual data strings. A different data pin is associated with each bit of the combined data string to transfer a datum for output from the memory module. Each signal line is connected to a control pin to receive an external signal for initiating transfer of one of the individual strings from one of the data memory circuits. The module further includes an additional memory circuit having a plurality of additional signal lines and a plurality of additional data lines. A first of the additional signal lines is wired in common with the signal line of a first one of the data memory circuits. A second of the additional signal lines is wired in common with the signal line of a second one of the data memory circuits. The additional memory circuit is responsive to transfer a bit of data along one of the additional data lines when an individual data string is transferred from one of the data memory circuits.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Dynamic random access memory arrays are generally described in U.
S.
Pat.
No.
4,081,701, issued to White, et al.
and assigned to Texas instruments Incorporated.
High density monolithic semiconductor memory devices constructed with multiple arrays formed thereon are well known in the art.
See, for example, U.
S.
Pat.
No.
4,636,986 to Pinkham, also assigned to Texas Instruments Incorporated and incorporated herein by reference, which illustrates a dual port, i.
e.
, both random and serial access, memory device such as provided for video RAM applications.
Normally, each of the multiple arrays comprises an equal number of active memory elements arranged in rows and columns.
Strings of address data are provided to common row and column decoders of the multiple arrays to simultaneously access a memory cell in each array.
Separate input/output buffers are associated with each array for parallel transfer of data, either stored or to be stored in the arrays, to and from an external source.
It has been proposed that the input to individual arrays on such a device can be controlled to selectively write data to less than all the memory cells having a common address.
To this extent, the U.
S.
Pat.
No.
4,636,986 to Pinkham discloses a write mask circuit for inhibiting data transfer to addressed memory locations and also teaches formation of a bit mapped video display memory device wherein writing of data into each of several arrays on the device is controllable with a separate Column Address Strobe signal CAS.
In the past the concept of restricting data input to less than all memory cells having a common address has been largely, if not solely, applied to dual port memory designed into graphic display systems because unique advantages are manifest when writing graphics data or providing enhanced graphics capabilities.
Moreover, while devices which include the write mask feature have become commercially popular, it is not known that video RAM designs which incorporate multiple Column Address Strobe control lines have generated any significant commercial interest



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