 Matrix display panel having alternating scan pulses generated within one frame scan period |
| It is an object of the present invention to provide a liquid crystal display panel having a high ... |
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| TDM system and method having time slot request signaling |
| Shown in FIG. 1 is an illustrative block diagram of a Time Division Multiplex (TDM) system 100 ... |
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| Vertical ramp automatic amplitude control |
| What is claimed is: 1. A method of producing a constant amplitude deflection ramp voltage over a ... |
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| Decision circuit operable at a wide range of voltages |
| What is claimed is: 1. A decision circuit, comprising: a first comparator which compares an input ... |
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| Communication path continuity verification arrangement |
| Time-slot Interchange Unit 11 Each of the line units transmits recurring frames each comprising 64 ... |
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| Switching regulator having low power mode responsive to load power consumption |
| A switching mode power converter monitors the level of power supplied to a load device. The ... |
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| Method for DRAM sensing current control |
| OF THE PREFERRED EMBODIMENTS OF THE INVENTION Turning first to FIG. 1, a portion of a prior art ... |
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| Sense amplifier power supply circuit |
| OF PREFERRED EMBODIMENT For the convenience of description, a sense amplifier power supply circuit ... |
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| Current monitors with independently adjustable dual level current thresholds |
| Current sensing circuits having independently adjustable dual-level trip thresholds for use in hot ... |
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Memory system having flexible addressing and method using tag and data bus communication
| Details |
Inventors: Lakhani, Vinod C.; Norman, Robert D.; Chevallier, Christophe J.;
Assignee: Micron Technology, Inc. (Boise, ID)
Primary Examiner: Verbrugge; Kevin
Assistant Examiner:
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner & Kluth, P.A..
A non-volatile memory system having a memory controller, an array of memory cells and a memory operation manager. The operation manager carries out memory program, read and erase operation upon receipt of program, read and erase instruction from the controller, typically over a system bus. The address block circuitry is provided in the manager which is capable of performing an memory operation on a single address or on multiple addresses depending upon the state of the address block circuitry as determined by the controller. Multiple addresses can be generated based upon a single address provided by the controller so that sectors of the memory can be programmed or read thereby simplifying memory operations and reducing the overhead of the memory controller. |
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DETAILED DESCRIPTION A memory system comprising a memory controller, an array of non-volatile memory cells and a memory operation manager is disclosed, with the array and operation manager preferably being implemented in an integrated circuit separate from the memory controller.
The memory controller is configured to issue memory program instructions, memory read instructions and memory erase instructions to the memory operation manager, preferably over a system bus.
The program instructions include program data information and program address information.
The memory operation manager is configured to carry out the memory program operations in response to receipt of one of the memory program instructions, memory read operations in response to receipt of one of the memory read instructions and memory erase operations in response to one of the memory erase instructions.
The operation manager further comprises a memory address block configured to control memory addresses used in memory read and program operations.
The memory address block contains a memory address derived from the read address information used during memory read operations and a memory address derived from the program address information used during memory program operations.
The memory address in the memory address block has a most significant address portion and a least significant address portion.
The least significant address portion of the memory block may be implemented, by way of example, in the form of a counter having an associated circuitry for enabling and disabling a counter increment function.
The memory address block is configured to modify the least significant address portion, with the modification being independent of the program address and read address information.
The memory operations manager further comprises a memory data block configured to control data used in the memory program operations.
In a typical memory read operation, it is possible to read multiple addresses of the array using a limited number of memory read instructions
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I/O Systems 
