Home | Links | Contact Us | More About Intellectual Property | Bookmark
Search patents:
Home I/O Systems Method-and-apparatus-for-an-enhanced-computer-system-interface

 Arbitration circuitry for deciding access requests from a multiplicity of components
We claim: 1. In a data-handling system with a multiplicity n=2.sup.m of components of different ...


 Paged memory management unit which locks translators in translation cache if lock specified in translation table
Accordingly, it is an object of the present invention to provide a mechanism which allows a paged ...


 Ensuring data integrity by locked-load and conditional-store operations in a multiprocessor system
In accordance with one embodiment of the invention, a high-performance processor is provided which ...


 Multiplexing communication card and scanning method for run-in testing
i The present invention provides a multiplexing communication card and scanning system for testing ...


 Fixture for motor controller power substrate and motor controller incorporating
In accordance with a first aspect of the invention, a fixture is provided for securing conducting ...


 Asynchronous digital time-division multiplexing system with distributed bus
What we claim is: 1. An asynchronous digital time-division multiplexing system, comprising (a) ...


 Method for executing overlays in an expanded memory data processing system
OF THE INVENTION FIG. 1 shows an Expanded Memory System (EMS). The system includes a one megabyte (...


 Robot program checking method
An object of the present invention is to provide a robot program checking method which permits ...


 Method of correcting machine position change
The present invention has been made in view of the aforesaid drawbacks, and an object thereof is to ...


 Communications controller utilizing an external buffer memory with plural channels between a host and network interface operating independently for transferring packets between protocol layers
OF ILLUSTRATIVE EMBODIMENT Referring to FIG. 2, the programmable (VLSI) data communication ...


 Method and apparatus for an enhanced computer system interface

Details
Inventors: Gajjar, Kumar; Shah, Kaushik S.; Trang, Duc H.;
Assignee: MTI Technology Corporation (Sunnyvale, CA)
Primary Examiner: Ray; Gopal C.
Assistant Examiner:
Attorney, Agent or Firm: Townsend and Townsend and Crew

An improved interface system based in part on the SCSI standard is provided. A single cable data bus simultaneously transfers several bytes of information between two devices. The interface system transfers multiple-byte commands, messages, status information or data in a single parallel transfer. A microsequencer is provided to permit data transfers across the interface without requiring burdensome attention from a processor in a device involved in the transfer.

DETAILED DESCRIPTION It is therefore an object of the present invention to provide an improved interface, based in part on the proposed SCSI-2 standard, by which multiple-byte commands, messages, and/or status information can be transferred in a single parallel transfer.
It is also an object of the present invention to provide a circuit for implementing the protocol of such an improved interface that can execute data transfers with minimal need for the attention of a device processor.
It is another object of the present invention to provide an improved interface that can be implemented using conventional SCSI integrated circuits and other commercially available components.
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing an interface (referred to hereafter as a SCSI-2E interface) comprising, in the preferred embodiment, a bus capable of simultaneously transferring at least 32 bits of data (plus at least 4 bits of parity data), and a microsequencer-driven interface unit for connecting devices to the bus.
A conventional 64-conductor cable has been found to be suitable for implementing the bus of this invention (referred to hereafter as a SCSI-2E cable), although cables of other widths may also be used.
In addition to having data and parity lines for transferring 32 bits of data (and their associated parity bits) in parallel, the SCSI-2E cable includes nine dedicated control lines.
The remaining lines provide paths for terminator power and ground.
The various data, parity, control, and other lines may be arranged within the cable as desired.
The SCSI-2E interface offers several advantages over the prior art.
For example, a single SCSI-2E cable replaces two prior art SCSI-2 cables (i.
e.
, cables A and B).
Also, the SCSI-2 A and B cables require separate "Request" and "Acknowledge" lines for each of the cables.
These two sets of Request and Acknowledge lines are required to synchronize the transfer of data on cables A and B during multiple-byte parallel data transfers



Related patents
  Data processing device having an expandable address space
In the aforementioned CPU, however, the address register has a length of 16 bits, and the memory to be referred to by the CPU has a capacity of 65,536 bytes (=2.sup.16 ...
  Single-chip mircocomputer with clock-signal switching function which can disable a high-speed oscillator to reduce power consumption
It is, therefore, an object of the present invention to overcome the problem existing in the conventional arrangement and to provide an improved single-chip ...
  Apparatus and method for reading helically recorded tracks and rereading tracks as necessary
OF THE DRAWINGS A helical-scan drive system 10 for recording on and reading magnetic tape 12 is illustrated in FIGS. 1 and 2. A drum 14 is angularly oriented with ...
  Tri-statable bus with apparatus to drive bus line to first level and then second level for predetermined time before turning off
An improved high speed bus with virtual memory capability is disclosed. The bus has particular application in computer systems which employ peripheral devices. The bus ...
  Method of compactly storing digital data
This invention provides a method of storing digital data in a compact manner which includes the steps of sequentially entering a plurality of digital data entries into a ...
  Method, device and microprocessor for selectively compressing video frames of a motion compensated prediction-based video codec
OF A PREFERRED EMBODIMENT A video sequence consists of individual images, or frames, of video data which are two dimensional representations of a three dimensional ...
  Bus control for small computer system interface with transfer indication preceding final word transfer and buffer empty indication preceding receipt acknowledgement
Accordingly, it is an object of the present invention to provide a SCSI bus control which has overcome the above mentioned defect of the conventional one. Another object ...
  Universal device for coupling a computer bus to a controller of a group of peripherals
We claim: 1. A universal device for coupling a computer bus of a computer to a controller of a group of peripherals connected to one another by a specific link to which ...
  Display interface system using buffered VDRAMs and plural shift registers for data rate control between data source and display
The present invention elates to a method and apparatus for permitting computer graphics systems designed to work with cathode ray tube displays to greatly expand their ...
  Monitoring plural process control stations
We claim: 1. A monitoring system for process controllers with error recognition and compensation in a monitoring function comprising: a plurality of self monitoring ...

0.014

Archive: All patents - Links

Copyright (c)2006 Eipa-patents.org - All rights reserved