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 Method and apparatus for data exchange between microprocessors

Details
Inventors: Hoptner, Wolfgang; Lotterbach, Gerhard; Perenthaler, Egbert; van Woudenberg, Jan F.; Zucker, Udo;
Assignee: Robert Bosch GmbH (Stuttgart, DE)
Primary Examiner: Harkcom; Gary V.
Assistant Examiner: Lacasse; Randy
Attorney, Agent or Firm: Frishauf, Holtz, Goodman & Woodward

A method and apparatus for data exchange between a master microprocessor and a slave microprocessor, in which the connection is a parallel bus and the data exchange requires a minimum of time. For this purpose, the data are transmitted in a predetermined sequence and in which the transmission-start identifier is a signal train generated by the master processor which is specifically associated with data transmission. Preferably, a master processor and a slave processor are interconnected by the parallel data bus, with buffer memories, such as latches, interposed. A toggle flip-flop is connected to the interrupt input of the slave processor in such a way that merely placing a specific instruction (i.e. command+data) on the bus simultaneously notifies the slave processor to prepare for the exchange of data, thereby saving time.

DETAILED DESCRIPTION FIG.
1 shows a master microprocessor 10, whose Input/Output (I/O) port is connected to the input of a latch 11.
A corresponding input of the latch 11 is also connected to the WRITE signal output WR of the master microprocessor 10.
The WRITE signal output WR also connects to the input of an OR-gate 14.
The output of the latch 11 leads to an I/O port of a slave microprocessor 12.
The READ-signal output RD of this slave microprocessor 12 is also connected to the latch 11.
A latch 13 is anti-parallel connected to the latch 11 and transfers signals from the I/O port of the slave microprocessor 12 to the I/O port of the master microprocessor 10.
The WRITE-signal output WR of the slave microprocessor 12 is connected to the latch 13.
Further, the READ-signal output RD of the master microprocessor 10 is connected to the latch 13.
In addition, a connection from the READ-signal output RD of the master microprocessor 10 leads to a further input of the OR-gate 14.
The output of the OR-gate 14 leads to an input of a toggle flip-flop 15.
The toggle flip-flop 15 changes its output condition upon each WRITE- or READ-command of the master microprocessor 10.
The output of the toggle flip-flop 15 is connected to the interrupt input INT of the slave microprocessor 12.
Further, a port P of the master microprocessor 10 is connected to a corresponding port P of the slave microprocessor 12.
Suitable microprocessors are the model 8051 from Intel Corp.
The structure and instruction set of this microprocessor are described in publicly available literature, are well known to those skilled in the art, do not per se form part of the present invention, and therefore need not be detailed in the present application beyond the details shown in FIG.
1.
Of course, other microprocessors can be used, especially others of the 8000 series from Intel.
The question of which I/O ports of the master microprocessor 10 or the slave microprocessor 12 are used for data input or output is a an arbitrary choice depending upon the programming of the microprocessors



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