Line camera for imaging object strips on photosensitive detector lines |
| What is claimed: 1. A line camera for imaging object strips on photosensitive detector lines, ... |
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Method for encoding SNMP summary objects |
| OF THE PREFERRED EMBODIMENT Referring to the drawings, especially FIG. 1, a concentrator 10 ... |
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Apparatus and method for modifying signals from a CPU to a memory card |
| A computer system and method of operation is provided wherein the memory controller of the system ... |
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Apparatus for reading and reproducing a color image |
| To achieve the foregoing objects, and in accordance with the purposes of the invention as embodied ... |
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Data recording system having unique end-of-recording and start-of-recording format indicators |
| OF THE INVENTION Broad Overview of the System While the present invention will be specifically ... |
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Microcomputer system for communication |
| In view of the aforementioned drawback, the inventors studied a system according to which, in the ... |
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Hierarchical storage management from a mirrored file system on a storage network segmented by a bridge |
| A solution to this problem is provided according to the teachings of the invention by mirroring the ... |
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Cell flow control in square-grid expanded ATM switch |
| Therefore, an object of the present invention is to provide a backpressure-type cell flow control ... |
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Latch mechanism for a header |
| With reference to the drawings, an electrical header 1 comprises a housing 2, electrical terminal ... |
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Non-volatile memory system |
| A non-volatile read/write memory module and a data processing system utilizing said module. The non-... |
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Method and apparatus for dispatching tasks requiring short-duration processor affinity
| Details |
Inventors: Clark, Carl E.; Frey, Jeffrey A.;
Assignee: International Business Machines Corp. (Armonk, NY)
Primary Examiner: Kriess; Kevin A.
Assistant Examiner: Spivak; Kevin
Attorney, Agent or Firm: Porter; William B., Michaelson; Peter L.
An application, executing on a first processing element in a MP system without an asymmetric feature, issues an instruction requiring that feature to complete. A program check interruption gives control to interrupt handlers, which create a high-priority, non-preemptable work unit control block and enters the dispatcher to enqueue the work unit on a processor-related queue associated with a second processing element having the asymmetric feature. When the dispatcher executes in the second processing element, it executes the non-preemptable work unit, which transfers control to the application at the point of interruption. Subsequently the application has only whatever processor affinity obtained prior to the program check. |
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DETAILED DESCRIPTION To achieve these and other objects, this invention provides a mechanism for efficiently redispatching a task from a first processor (lacking a required resource) to a second processor (with the required resource), without requiring that the task continue to execute on the second processor after its initial dispatch there. The MVS embodiment is to create a set of processor-related dispatcher queues, which are scanned early by a dispatcher executing in a processor ready for work. When a task is interrupted by a program check because a resource required to execute the instruction is not on that processor, the interrupt handling mechanism suspends the task, making it ineligible to be dispatched, and enqueues an SRB on the processor-related queue for a processor having the required resource. The processor having the resource then resumes processing of the interrupted task via the SRB RESUME mechanism (at the point of interruption) on a subsequent scan for work. Because there is no setting of task affinity with this mechanism, there is no need to "unset" affinity--i. e. , the task will automatically be dispatchable on any free processor after its next interruption. This characteristic makes the invention suitable for "transient" affinity requirements (e. g. , a cryptographic instruction requiring a cryptographic feature). Typically, a task executing a crypto function (encipher/decipher) will not likely execute another such instruction "soon". Therefore, giving the task affinity for the processor having the crypto feature unnecessarily limits the system's load balancing ability, while requiring an overt action ("unsetting" affinity) is wasteful of processing time. )
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