Home | Links | Contact Us | More About Intellectual Property | Bookmark
Search patents:
Home I/O Systems Method-and-apparatus-for-local-area-communication-networks

 Dynamic logic having power-down mode with periodic clock refresh for a low-power graphics controller
A controller chip has dynamic logic which is driven by a suspendable clock. Power is reduced in a ...


 Timing apparatus and timing method for wrapper cell speed path testing of embedded cores within an integrated circuit
What is claimed is: 1. An integrated circuit comprising: an embedded core which is adapted to ...


 Media connect module for portable computer
The present invention is directed to a module which may be connected to an I/O port of a notebook ...


 Initializing a read pipeline of a non-volatile sequential memory device
A sequential memory device having a read pipeline data structure is provided that is initialized ...


 Data read circuit for use in semiconductor storage apparatus of CMOS memory
An essential object of the present invention is to provide a data read circuit for use in a ...


 Data communications system with improved asynchronous retiming circuit
The present invention relates to an improved asynchronous data communications system including a ...


 Line driver circuit
Accordingly, an object of the present invention is to provide a line driver circuit which can ...


 Non-coherent pattern detection
The present invention is directed to a digital non-coherent pattern detection scheme in which ...


 Decoder for three level coded data
Accordingly, it is an object of the invention to provide improved means for converting a three ...


 Time-division multiplex communication transmission apparatus
It is an object of the present invention to provide a time-division multiplex radio transmission ...


 Method and apparatus for local area communication networks

Details
Inventors: Ulug, Mehmet E.;
Assignee: General Electric Company (Schenectady, NY)
Primary Examiner: Olms; Douglas W.
Assistant Examiner: Scutch, III; Frank M.
Attorney, Agent or Firm: Burgujian; Richard V., Davis, Jr.; James C., Webb, II; Paul R.

A bus accessing method and apparatus for the practice thereof in a communication network is disclosed. The network comprises a transmit bus, a receive bus, a plurality of BIUs connected between the transmit and receive buses and a head-end for directing signals leaving the transmit bus onto the receive bus. Each information packet has two control bytes respectively following the start frame delimiter and preceding the end frame delimiter. Each BIU includes means for comparing the bits it receives with the bits as transmitted thereby, a bit mismatch indicating that a downstream BIU has been preempted. During packet transmission, upon detecting a bit mismatch, the transmitting BIU sets one or both control bytes to "1010" so that receiving BIUs in the network are apprised of the preemption. Subsequently, preempted BIUs transmit their packets in accordance with a predetermined protocol, each packet so transmitted having its control bytes set to "1010". In the case where there are no preempted BIUs, each BIU transmits a packet with the control bytes set to "0101", thereby apprising receiving BIUs that there are no preempted BIUs. Each free mode BIU with a packet to transmit commences transmission substantially immediately following the last transmitted packet if there are no preempted BIUs in the system and the buses are idle.

DETAILED DESCRIPTION In accordance with the present invention, there is provided a bus accessing method and a communication network for practicing the method.
The communication network comprises a transmit bus, a receive bus, means for directing signals leaving the transmit bus onto the receive bus and a plurality of BIUs coupled between the transmit and receive buses.
Each BIU is coupled to a user device for which it transmits and receives information packets on the transmit and receive buses, respectively.
Each BIU includes means for detecting signals originating from an upstream direction away from the directing means on the transmit bus, means for detecting signals on the receive bus and means for comparing bits received with the bits of an information packet as transmitted thereby.
The comparing means provides a collision signal upon detecting a bit mismatch, the mismatch indicating that a downstream BIU has been preempted and entered a preempted mode.
Each information packet includes a control portion which when set to a predetermined value, indicates to BIUs receiving the packet on the receive bus that at least one BIU in the system is in the preempted mode.
Each BIU includes means for setting the control portion to the predetermined value, indicating a preemption, upon its respective comparing means providing the collision signal.
Each BIU in the preempted mode gains access to the transmit bus in accordance with the predetermined P-BID protocol and transmits its information packet with the control portion set to the predetermined value indicating the preemption.
Each BIU receiving a packet on the receive bus, upon determining that the control portion is set, is apprised there is at least one preempted BIU in the system which will gain bus access to transmit its packet, in accordance with the P-BID protocol.
In the case where there are no preempted BIUs in the system, each BIU transmitting a packet does so with the control portion not set.
Each BIU receiving such a packet is apprised that there are no preempted BIUs in the system



Related patents
  Method of operation of a D.C. electric-arc furnace with bottom electrode and refractory part for its implementation
The object of the invention is to limit or even prevent wear on the upper shell ring, in order to extend the lifetime of the shell rings and of the hearth in its ...
  Synchronization of time-of-day clocks in a distributed processing network system
It is an object of the present invention to provide improved means for synchronizing station time-of-day clocks in a distributed processing system. It is another object ...
  Information transfer system
The present invention is an information transfer system which transfers altered or new information to a selected one of a plurality of circuit stages via a data without ...
  Semiconductor memory device
An object of the present invention is to allow high speed access operation in a semiconductor memory device including a plurality of memory cell regions without increase ...
  Programmable memory controller for power and noise reduction
In accordance with the present invention, there is provided an apparatus for providing memory address and control signals to single in-line memory module (SIMM) ...
  Layout of a semiconductor memory device
An object of the present invention is to ensure proper operation of a sense amplifier, and to reduce sensing time and improve sensitivity thereof. Another object of the ...
  Integrated circuit module having on-chip surge capacitors
In accordance with the present invention, capacitance filtering is provided for a circuit having an array of similar semiconductor circuit devices, such as a SIMM (...
  Floating gate nonvolatile memory with distributed blocking feature
FIG. 2 illustrates in block diagram form the physical die layout of a flash EPROM 50, which implements a preferred embodiment of the present invention. Flash EPROM 50 ...
  Dram wtih open digit lines and array edge reference sensing
The above mentioned problems with integrated memories and other problems are addressed by the present invention and which will be understood by reading and studying the ...
  Method of and circuitry for generating staggered restore timing signals in block partitioned DRAM
An object of the present invention is to solve the above described problems and to provide a dynamic type semiconductor memory device capable of reducing peak current ...

0.054

Archive: All patents - Links

Copyright (c)2006 Eipa-patents.org - All rights reserved