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Details
Inventors: Sasson, Steven J.;
Assignee: Eastman Kodak Company (Rochester, NY)
Primary Examiner: Oberley; Alvin E.
Assistant Examiner: Mengistu; Amare
Attorney, Agent or Firm: Parkhurst, Wendel & Rossi

The invention provides a framestore architecture that permits direct addressing of digital image data in order to generate rotated image. The framestore architecture permits direct addressing at standard video sampling rates in order to generate rotated image data in real time. More specifically, in a preferred embodiment, the present invention provides an input unit for latching input pixel data in a predetermined sequence; a storage unit, including a plurality of storage devices, coupled to the input unit for storing the input pixel data latched by the input unit; an output unit coupled to the storage unit for retrieving the pixel data stored in the storage unit and generating an output pixel data stream in accordance with a predetermined sequence; an addressing unit coupled to the storage unit for addressing the storage devices included therein; and a control unit for controlling the overall operation of the input unit, the storage unit, the output unit and the addressing unit in a write operation mode and a read operation mode, wherein the input pixel data is stored in the storage devices in the write operation mode such that consecutive pixel data retrieved during the read operation mode is not stored in the same storage device.

DETAILED DESCRIPTION The invention provides a framestore architecture that permits direct addressing of digital image data in order to generate rotated image.
The framestore architecture permits direct addressing at standard video sampling rates in order to generate rotated image data in real time.
More specifically, in a preferred embodiment, the present invention provides and input unit for latching input pixel data in a predetermined sequence; a storage unit, including a plurality of storage devices, coupled to the input unit for storing the input pixel data latched by the input unit; an output unit coupled to the storage unit for retrieving the pixel data stored in the storage unit and generating an output pixel data stream in accordance with a predetermined sequence; an addressing unit coupled to the storage unit for addressing the storage devices included therein; and a control unit for controlling the overall operation of the input unit, the storage unit, the output unit and the addressing unit in a write operation mode and a read operation mode, wherein the input pixel data is stored in the storage devices in the write operation mode such that consecutive pixel data retrieved during the read operation mode is not stored in the same storage device.



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