Method and apparatus for transferring data in parallel from a smaller to a larger register

DETAILED DESCRIPTION OF THE DRAWING Referring to FIG.
1, there is provided in a prior known apparatus for transferring data in parallel from a smaller to a larger register designated generally as 1, a 16 stage data register 2, a plurality of 16 latches designated generally as 3 and a 32 stage data register designated generally as 4.
In the register 4 there is provided a first set of 16 stages 5 and a second set of 16 stages 6.
Typically, the stages 5 and 6 comprise D-flip-flops.
The register 2 is coupled to a source of clock pulses 7 by means of a line 8.
The latches 3 and the 32 stages in the register 4 are coupled to the source of clock pulses 7 through a divide-by-2 divider 9 by means of a line 10.
The 16 stages of the register 2 are coupled to the inputs of the 16 latches 3 and to the inputs of the second set 6 of 16 stages in the register 4 by means of a 16 line data bus 15.
The outputs of the 16 latches 3 are coupled to the inputs of the first set of 16 stages 5 of the register 4 by means of a 16 line bus 18.
The outputs of the register 4 are provided on a 32 line bus designated generally as 14.
Referring to FIG.
2, there is provided a plurality of timing diagrams (a)-(g).
Diagrams (a), (b) and (d)-(g) show the timing of clock and data signals in the apparatus of FIG.
1.
These diagrams and diagram (c) show the timing of clock and data signals in the apparatus of FIG.
3.
In diagram (a) there is shown a plurality of clock pulses 21 which are used for clocking data out of the register 2.
In diagram (b) there is shown a plurality of clock pulses 22 which are used for clocking data into and out of the latches 3 and register 4.
It will be noted that the rate of the pulses 21 is twice the rate of the pulses 22 and that each of the pulses 22 have a leading positive- going edge 23, as shown by an arrow, and a trailing negative-going edge 24.
In diagram (c) there is shown the pulse used in the apparatus of FIG.
3, but not in apparatus of FIG.
1.
In diagram (d) there is shown a representation of a plurality of pairs of 16 parallel bit words, each pair comprising a first word 25 (solid lines) and a second word 26 (dash lines)