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Home I/O Systems Method-and-system-for-dynamically-assigning-addresses-to-an-input-output-device

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 Method and system for dynamically assigning addresses to an input/output device

Details
Inventors: Beardsley, Brent Cameron; Meritt, Allan Samuel; Paulsen, Michael Aloysius; Yudenfriend, Harry Morris;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Shin; Christopher B.
Assistant Examiner:
Attorney, Agent or Firm: Victor, Esq.; David W. Konrad Raynes & Victor LLP

Disclosed is a system for dynamically assigning alias addresses to base addresses referencing an I/O device, such as a direct access storage device (DASD). In the system, at least one base control block indicates a base address and a plurality of alias control blocks indicate a plurality of alias addresses. Each control block is associated with an address for addressing an I/O device. A processing unit, such as a host computer system, processes at least one alias control block associated with the I/O device and determines a base control block associated with the I/O device with which the alias control blocks are associated. The processing unit then binds at least one alias control block to the determined base control block. The bound base and alias control blocks provide different addresses to address the same I/O device. Further, the bound base and alias addresses address the same I/O device for subsequent I/O operations until the processing unit detects a reassignment of the association of base and alias addresses.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, several embodiments of the present invention.
It is understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.
Hardware and Software Environment FIG.
2 illustrates a preferred hardware and software environment in which preferred embodiments are implemented.
A host system 16 is in communication with a storage controller 18.
The host system 16 views the storage controller 18 as a channel subsystem 20 that interfaces the CPUs 24a, b in the host 16 with I/O devices 26a, b, c.
The host may have more than the two CPUs 24a, b shown in FIG.
2.
Moreover, in preferred embodiments the CPUs 24a, b are capable of multi-tasking and each CPU 24a, b can simultaneously issue parallel execution paths.
The channel subsystem 20 is the host 16 view of paths to the I/O devices 26a, b, c as represented by subchannels 32a, b, c.
The host 16 would execute channel commands to manage the operation of the I/O devices 26a, b, c.
Each I/O device 26a, b, c may be a particular volume of a direct access storage device (DASD).
The storage controller 18 controls access to the I/O devices 26a, b, c.
As discussed, the storage controller 18 may include multiple logical subsystems (LSSs), i.
e.
, control unit images, wherein each LSS may address up to 256 devices.
In alternative embodiments, there may actually be multiple storage controllers providing communication with different I/O devices 26a, b, c.
The channel subsystem 20, which may be a construct maintained in the main memory 30 of the host 16, includes subchannels 32a, b, c that execute operations for the channel subsystem 20.
Channel paths 35 provide data communication between the host 16 and storage controller 18.
The host 16 maintains unit control blocks (UCB) that include device (volume) identification information and a device number



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