DETAILED DESCRIPTION An invention for optimized data presentation to an external memory interface bus is provided.
The embodiments of the present invention monitor the bits in the data, and based on the type of bits that the majority of the bits in the data belong to, determine whether the data are to be encoded.
When the data are encoded, the status bit is set to a particular logical value.
After that, the parity generator counts the number of logic high values, e.
g.
, 1s in the data, including the status bit, and sets the parity bit to a one or a zero based on whether the number of logical high values in the data is even or odd.
The parity generator generates the parity bit in series with the encoder scheme, which not only helps to ensure integrity of the data but also ensures the integrity of the status bit.
FIG.
1 shows a general block diagram of a PLD 100 in accordance with an embodiment of the present invention.
PLD 100 includes processor 102, programmable logic circuitry 104, programmable interconnect circuitry 106, and memory data manager 108.
PLD 100 illustrated herein may include other blocks and circuitry, as persons of ordinary skill in the art understand.
Examples of such circuitry include clock generation and distribution circuits, communication circuitry and/or controllers, input/output circuitry, and the like.
As one skilled in the art should understand, the PLD 100 may include more than one processor.
Additionally, processor 102 may couple to other blocks and circuits within or external to the PLD 100.
Processor 102 may receive data from circuits within or external to the PLD 100 and process the information in a variety of ways.
Programmable logic circuitry 104 may include a varying number of logic elements (LEs) (not shown), which are basic building blocks of a PLD.
Programmable logic circuitry may further include look up tables (LUT), product-term logic, multiplexers, logic gates, registers, memory and the like, that are necessary elements that perform desired logic functions
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I/O Systems 
