Method and system for supporting non-deterministic burst lengths in a memory system employing extended data out(EDO)DRAM

DETAILED DESCRIPTION The problems outlined above are in large part solved by a computer memory system in accordance with the present invention.
Broadly speaking, the present invention contemplates a computer system employing EDO DRAM and capable of supporting memory burst accesses across memory bank boundaries while avoiding data bus contention.
The invention provides a memory system with a plurality of memory banks employing EDO DRAM.
The memory banks are controlled by a memory controller device.
The memory controller device supplies the necessary control signals to the memory such as RAS, CAS, and memory write enable (MWE).
The memory controller includes logic to generate bank select signals indicating which memory bank is selected for the current access cycle.
The memory controller further includes comparison logic that compares the bank select signals for the current access cycle to the bank select signals from the previous access cycle.
When a different bank is accessed in the current cycle than was accessed in the previous cycle, the comparison logic asserts a bank traversal signal.
The bank traversal signal is received by CAS controller logic within the memory controller.
Delay logic in the CAS controller logic delays assertion of the appropriate CAS signal(s) when the bank traversal signal is asserted.
The length of the delay may be programmably selected.
Disabling logic within the memory controller also receives the bank traversal signal and asserts a disable signal to turn off the output drivers of the previously selected memory bank.
The invention contemplates the use of the memory write enable (MWE) signal for EDO DRAM wherein the MWE signal is pulsed active thereby turning off the EDO DRAM output drivers.
In one embodiment of the invention, the comparison logic may comprise logic for latching the bank select signals.
The latched bank select signals store the state of the bank select signals for comparison in the next access cycle.
The comparison logic preferably includes logic for comparing the current bank select signals to the latched bank select signals, and logic for generating the bank traversal signal when the comparison logic indicates access to a different bank