 Signal-processing multiprocessor system |
| It is an object of the present invention to provide a signal-processing system which makes it ... |
|
| Microcoded microprocessor with shared ram |
| The present invention is a system for utilizing a single RAM array as a control store for microcode,... |
|
| Buffer memory device capable of memorizing operand and instruction data blocks at different block sizes |
| What is claimed is: 1. In a buffer memory device intermediate between a central processing unit and ... |
|
| Data transfer control unit permitting data access to memory prior to completion of data transfer |
| What is claimed is: 1. A data transfer control unit comprising: (a) first address register means ... |
|
| Voltage comparator |
| An object of the invention is to provide a voltage comparator, which can operate efficiently with a ... |
|
| Logarithmic transformation circuitry for use in semiconductor integrated circuit devices |
| It is therefore an object of the present invention to provide a new and improved logarithmic ... |
|
| Low-voltage CMOS comparator |
| In general, the invention features a CMOS comparator which includes a capacitor connected in an ... |
|
| Compact comparator |
| FIG. 1 shows a first embodiment of the invention. The comparator circuit 100 has first and second ... |
|
| Synchronizing circuit for receiving an asynchronous input signal |
| It is an object of the present invention to provide a synchronizing circuit capable of reducing the ... |
|
| Virtual network architecture for connectionless LAN backbone |
| FIG. 1 provides a conceptual overview of a network in which the present invention operates. The ... |
|
|
Method for DRAM sensing current control
| Details |
Inventors: Foss, Richard C.; Gillingham, Peter B.; Harland, Robert; Mitsuhashi, Masami; Wada, Atsushi;
Assignee: Mosaid Technologies Incorporated (Kanata, CA)
Primary Examiner: Dinh; Son
Assistant Examiner:
Attorney, Agent or Firm: Pascal & Associates
A DRAM having a plurality of bit lines and associated sense amplifiers, the bit lines being arrayed across an integrated circuit chip and the sense amplifiers being disposed in a row, a pair of low resistance power supply conductors extending in parallel with the row for carrying logic high level and logic low level voltages, sense amplifier enabling signal conductors extending across the chip accessible to the sense amplifiers, apparatus for coupling sense inputs of the sense amplifiers to the power supply conductors, and apparatus coupling the sense amplifier enabling signal conductors to the apparatus for coupling sense inputs, for enabling passage of current resulting from the logic high level and low level voltages to the sense amplifiers. |
|
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION Turning first to FIG.
1, a portion of a prior art bit line and sense amplifier circuit is shown.
Bit storage capacitors 1A and 1B are coupled through field effect transistors (FETs) 2A and 2B to complementary bit lines BL and /BL of a folded bit line.
The gates of transistors 2A and 2B are connected to word lines WL.
sub.
n and WL.
sub.
n+1 in a well known manner.
A sense amplifier 3 is connected to the bit lines also in a well known manner.
The bit lines are coupled to databuses DB and /DB via FETs 4A and 4B.
The sense amplifier 3 is formed of a pair of N-channel transistors having their series connected source-drain circuits connected across the bit lines of the folded bit line, their junction being connected to an active low logic level source /.
phi.
.
sub.
s, and a pair of P-channel FETs having their series connected source-drain circuits connected across bit lines BL and /BL, their junction being connected to an active high level source .
phi.
.
sub.
R.
The gates of the N and P-channel transistors connected to a first bit line are connected together and to the other bit line, and the gates of the transistors connected to the other transistor are connected together and to the first bit line.
In operation a transistor e.
g.
2B is enabled from a word line, and the charge, representing a bit, stored on a capacitor e.
g.
1B is dumped to the associated bit line /BL.
This creates a voltage differential between bit lines BL and /BL which appears across sense nodes SA and SB.
When the logic levels /.
phi.
.
sub.
s and .
phi.
.
sub.
R are applied to the sense amplifier 3, the voltage differential causes the circuit to latch, applying the full logic levels of /.
phi.
.
sub.
s and .
phi.
.
sub.
R to the bit lines.
This restores the charge on the capacitor 1B to full logic level.
Upon enabling of the transistors 4A and 4B by the signal /.
phi.
.
sub.
yi, the resulting full logic level on the bit lines is applied to the databuses DB and /DB.
Associated with each bit line is an inherent capacitance 5A and 5B, which results from the length and breadth of the bit line track on the semiconductor and the substrate
|
|
I/O Systems 
