Method for design optimization using logical and physical information

DETAILED DESCRIPTION The present invention provides a method for optimizing a layout design, which minimizes the optimization cycle by incorporating interconnect wiring delays and performing logic optimization in the placement and routing operations.
In one embodiment of the present invention, the method includes the steps of: (a) obtaining a first placement of circuit elements of a gate-level circuit; (b) providing routing between circuit elements; (c) performing a timing analysis to provide estimates of interconnect delay between circuit elements; (d) performing a logic optimization operation to obtain a second gate-level design based on a cost function.
The steps (a)-(d) are reiterated until the cost function becomes less than a predetermined threshold.
In one embodiment, a clustering of circuit elements allows circuit elements having high connectivity amongst them to be kept together and thus placed in close proximity of each other, while minimizing inter-cluster interconnect wiring delays.
In that embodiment, the method is iterated over an outer-loop in which each iteration divides circuit elements into clusters and applies steps (b) through (e) on the clusters until the cluster includes only primitive circuit elements.
In one embodiment, the logic optimization operation, which is performed concurrently with the placement and routing operations, (i) reassigns circuit elements between clusters, (ii) inserts or deletes signal buffers between circuit elements (iii) synthesizes alternative implementations of logic functions.
The method of the present invention can be implemented in a parallel processing design automation system to achieve high performance.
Such a parallel processing system includes (a) multiple central processing units (CPUs) executing independently of each other; (b) a shared memory accessible by each CPU for holding data structures of the integrated circuit design; and (c) a control program managing a task list which specifies tasks for optimizing the integrated design