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Home I/O Systems Method-for-executing-overlays-in-an-expanded-memory-data-processing-system

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Details
Inventors: Sherman, Arthur M.; Walling, Lonnie S.;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Levy; Stuart S.
Assistant Examiner: Elmore; Reba I.
Attorney, Agent or Firm: Perman & Green

A method includes the steps of differentiating Overlays each into a code portion and into a data portion, storing the data portions within a CPU directly-accessible memory, storing the code portions within a memory not-directly accessible by the CPU, and swapping a required code portion into the directly-accessible memory for execution by the CPU such that the swapped-in code portion has access to a plurality of the data portions stored within the directly-accessible memory.

DETAILED DESCRIPTION OF THE INVENTION FIG.
1 shows an Expanded Memory System (EMS).
The system includes a one megabyte (1024K) physical memory 1 address space and a typically larger, for example up to 32 megabytes, expanded memory 2 address space.
The physical memory 1 is coupled to and is directly accessible by a CPU that reads and writes the memory 1.
The expanded memory 2 provides additional memory beyond a maximum addressable memory limit of the CPU.
For example, microprocessors such as the 8086, 8088 and the 80286, operated in the real mode, are capable of physically addressing up to 1024K bytes of memory.
The expanded memory is therefore accessed through a page frame 3 "window", or predetermined range of addresses, located within the directly accessible 1024K physical address range.
In the example shown the page frame 3 occupies the range of addresses between 768K and 960K but this range of addresses need only be 64K bytes.
In other embodiments the page frame 3 can occupy other ranges of addresses.
The expanded memory 2 is partitioned into segments referred to as logical pages 4 each of which is typically 16K bytes in length.
The logical pages 4 are accessed through the physical block of memory associated with the page frame 3.
The page frame 3 contains a plurality, typically four, directly accessible physical pages 5, each of the physical pages 5 also being typically 16K bytes in length.
In the presently preferred embodiment of the invention only one physical page 5 is used.
It should be noted that the physical page(s) 5 can be mapped at address locations other than those illustrated, such as within the lower 640K of memory.
In operation the EMS maps a logical page 4 of expanded memory 2 into a particular one of the physical pages 5 of the page frame 3, thereby providing the CPU direct access to the logical page 4.
The operation of one particular type of EMS that is particularly suitable for use with a presently preferred embodiment of the invention is set forth in a publication "Lotus



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