 Mechanism for measuring the service times of software and hardware components in complex systems |
| The mechanism according to the present invention is used for measuring the service times required ... |
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| Communications network and method which implement diversified routing |
| What is claimed is: 1. A method of sending information through a network having a plurality of ... |
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| Method of determining the topology of a network of objects |
| OF THE PREFERRED EMBODIMENTS The invention will be described by reference to its theory of ... |
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| Enabling target servers to control determination of full user synchronization |
| It is a general object of this invention to provide full synchronization on demand by a managed ... |
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| Instrument housing |
| FIG. 3 illustrates the components of the basic instrument housing 10 in accordance with this ... |
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| Release apparatus for computer mass storage devices |
| It is an object of the present invention to provide an apparatus for efficiently removing mass ... |
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| Cooling of electronic equipment cabinets |
| FIG. 1 illustrates an embodiment of the invention. The cabinet 10 includes a housing 11 and four ... |
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| Form factor adaptor |
| The present form factor adaptor overcomes many disadvantages of the prior form factor conversion ... |
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| Printed circuit board mounting cage |
| In carrying out principles of the present invention in accordance with a preferred embodiment ... |
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Method for selectively saving/restoring first registers and bypassing second registers in register units based on individual lock/unlock status thereof
| Details |
Inventors: Koizumi, Shinobu;
Assignee: Hitachi, Ltd. (Tokyo, JP)
Primary Examiner: Lee; Thomas C.
Assistant Examiner: Kim; Sang Hui
Attorney, Agent or Firm: Fay, Sharpe, Beall, Fagan, Minnich & McKee
In a data processing system having a central processing unit including a register file for storage of often-used data, a method and system is provided for saving and restoring the contents of the register file from the main memory only when necessary. Each register unit in the register file includes a register protection flag, a save area pointer and a plurality of general purpose registers. The register protection flag is coded to identify if the register unit is in actual use by having contents stored in any of the general purpose registers. Before saving or restoring the register unit, its register protection flag is checked, and only if the flag indicates actual use is the saving or restoring performed. |
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DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings wherein the showings are for purposes of illustrating preferred embodiments of the invention only and not for purposes of limitation thereto, the FIGURES show a data processing system and method in which a central processing unit has a register file whose contents are saved and restored in and from a main memory only a minimal number of times for improved program processing Speed.
More particularly, FIG.
1 shows a block diagram of a computer system made in accordance with the present invention.
The computer system is comprised of a central processing unit (CPU) 1, a main memory 2, and an address bus 3 and a data bus 4 for connecting them.
The CPU 1 includes an instruction decoder (ID) 5, a microcontrol unit (MU) 6, an execution unit (EU) 7, a bus controller 8, and two internal buses 9, a microcontrol bus 10 and a microinstruction bus 11 for connecting them.
The instruction decoder (ID) 5 decodes an instruction given to the CPU 1, and controls the execution of the instruction.
More specifically, the content (instruction code) of that address of the main memory 2 which is indicated by an instruction pointer (IP) 12 is loaded in an instruction buffer (IB) 13, the operands of the instruction are computed, and the resultant values are set in operand registers (OR0) 14 and (OR1) 15.
Further, the ID 5 instructs the MU 6 through the microcontrol bus 10 to start a microprogram sequence corresponding to the instruction code.
The ID 5 includes a decoder controller 16 which executes the above control.
The microcontrol unit (MU) 6 controls the sequence of the executions of microinstructions, such as branch, recursion and end, in a microprogram.
The MU 6 includes a microprogram ROM 17 which holds the microprogram sequence corresponding to the instruction, and a microsequencer 18 which is a control circuit.
In addition, the microinstructions to be executed are given to the EU 7 through the microinstruction bus 11.
The execution unit (EU) 7 executes the microinstructions provided by the MU6
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I/O Systems 
